Author(s):	Steffen Trumtrar
Location	UB2.252A (Lameere)
Date	feb Sat 01	Days Raw Files
Start	12:00	First Raw Start	error-in-template
Duration	00:30:00	Offset	None
End	12:30	Last Raw End
Chapters
Total cuts_time	None min.

https://fosdem.org/2014/schedule/event/socs_fpgas/
raw-playlist raw-mp4-playlist encoded-files-playlist mp4 svg png

assets release.pdf SoCs_FPGAs.json
logs
Admin: episode episode list cut list raw files day marks day marks day image_files

State:	--------- borked edit encode push to queue post richard review 1 email review 2 make public tweet to-miror conf done
Locked:	clear this to unlock
Locked by:	user/process that locked.
Start:	initially scheduled time from master, adjusted to match reality
Duration:	length in hh:mm:ss
Name:	Video Title (shows in video search results)
Emails:	email(s) of the presenter(s)
Released:	Unknown Yes No has someone authorised pubication
Normalise:
Channelcopy:	m=mono, 01=copy left to right, 10=right to left, 00=ignore.
Thumbnail:	filename.png
Description:	<p>Xilinx and Altera both took the next step in integrating System on Chips (SoC) with Field Programmable Gate Arrays (FPGA): put them both on the same die and connect them with a high speed interface. This talk will describe the Altera Socfpga platform, its current support in the mainline Linux kernel, lessons learned in using the vendor supplied information and what this new kind of dual core CPU and FPGA alliance opens up for possibilities in low latency RT applications.</p> markdown
Comment:	not recorded due to problems with laptops enc error: No cutlist found. enc error: No cutlist found. enc error: No cutlist found. production notes