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Name: Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
--client fossi --show latch_2019 --room revolution 14817 --force
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Author(s):	Matthew Ballance
Location	Revolution Hall
Date	may Sun 05	Days Raw Files
Start	10:30	First Raw Start	12:07
Duration	0:30:0	Offset	1:37:13
End	11:00	Last Raw End	13:07
Chapters	00:00 0:13:27 0:20:53
Total cuts_time	25 min.

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Description:	Open source and industry have a long history of overlapping in the software space. Engineers from industry often work on open-source software in their free time, open source software is used in commercial applications, and students use open-source software to learn about how real software is designed, developed, and tested. A key enabler is that open-source software is largely developed and tested in the same way that commercial software is. Commercial software development often uses commercial tools with features beyond what is available to open-source developers, but the large degree to which techniques and methodologies are aligned facilitates collaboration. What of open source silicon? We certainly use standard design languages (Verilog and VHDL). But verification in the industry is typically done with SystemVerilog and UVM, and SystemVerilog tools are out-of-reach for the open-source silicon developer. Or, are they? As it turns out, there are both open-source and freely-available tools, and educational resources, to help open-source silicon developers create verification environments that align with commercial verification practices. This talk will present tools and educational resources for creating SystemVerilog and UVM testbench environments, as well as techniques for creating SystemVerilog and UVM testbenches for open-source silicon that both work with freely-available tools and scale to take advantage of the features of commercial simulation tools. markdown
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