veyepar: Using CVA6 in Architecture Education

Author(s):	Ethan Sifferman
Location	UCSB Henley Hall room 1010
Date	apr Sat 01	Days Raw Files
Start	13:27	First Raw Start	12:57
Duration	00:3:00	Offset	0:29:01
End	13:30	Last Raw End	14:27
Chapters	00:00
Total cuts_time	3 min.

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Description:	Computer architecture students now have an incredible breadth of cores to learn from because of the ever-increasing list of open-source cores that are well-structured, are synthesizable, use modern SystemVerilog, and have good documentation. Of the most popular open-source RISC-V cores, CVA6, is the perfect candidate for an advanced architecture course because of its 6-stage pipeline, dynamic branch predictor, L1 cache, scoreboard unit, and virtual memory support. UC Santa Barbara has created a set of advanced architecture labs with questions ranging from locating where certain behaviors are implemented in CVA6’s code, to adding additional features to CVA6, and to writing and running assembly files through a CVA6 simulation. We also provide several CVA6-compatible example assembly files and gcc commands that demonstrate how to set up the FPU, benchmark the branch predictor, switch between RISC-V privilege levels, and enable virtual memory with a basic OS. Open-source hardware’s growing popularity has helped UC Santa Barbara tremendously in offering hands-on experiences to students. markdown
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