veyepar: bsg_tag: A minimal open-source ASIC configuration bus

Author(s):	Dan Petrisko
Location	UCSB Henley Hall room 1010
Date	mar Fri 31	Days Raw Files
Start	14:00	First Raw Start	13:02
Duration	00:20:00	Offset	0:57:59
End	14:20	Last Raw End	15:04
Chapters	00:00 0:10:43 0:13:34 0:13:35 0:15:04 0:16:32
Total cuts_time	19 min.

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Description:	Digital designs often contain a large number of configuration registers needed to bring up the chip. These may represent clock sources, resets, enable bits, global id settings, IP modes, or other static configuration. To avoid bootstrapping problems, it's necessary to be able to control these registers from outside of the chip itself. For reset and bringup procedures, designs require precise and robust sequencing. However, GPIOs can be extremely expensive in terms of area (especially on small designs in an MPW run), so controlling these registers must be done with as few pins as possible. Complex designs can have hundreds or thousands of configuration bits, so there needs to be a higher level protocol which can scale from this minimal number of actual I/Os. We present bsg_tag, which is a decentralized source-synchronous bus and protocol layer for ASIC configuration. bsg_tag creates a powerful abstraction where with a few pins, you can reach inside your chip at high bandwidth and set any register while the chip is running, no matter what clock domain that register is in. From this abstraction, we can build many more powerful mechanisms. Unlike other standard configuration methodologies, bsg_tag is non-invasive, requiring minimal RTL changes and integrates seamlessly into existing IP blocks. bsg_tag is fast, robust and gracefully handles synchronized crossing into local clock domains. bsg_tag is battle-tested has been used in many academic and commercial tapeouts, usually being the first functionality tested in a bringup procedure. This talk will discuss the physical and protocol layers of bsg_tag, as well as and demo software infrastructure built up for simple interactive debugging. Come learn how to simplify bringup of your next SoC! markdown
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