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Accelerating Chisel Development
--client
fossi
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latch_2023
--room henley1010 15227 --force
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Marks
Author(s):
Jack Koenig
Location
UCSB Henley Hall room 1010
Date
mar Fri 31
Days Raw Files
Start
17:00
First Raw Start
16:04
Duration
00:20:00
Offset
0:55:40
End
17:20
Last Raw End
18:04
Chapters
00:00
0:21:56
Total cuts_time
35 min.
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For over a decade, Chisel has made designers more productive through the power of parametrizable generators. Chisel 3 introduced the FIRRTL compiler and a period of measured development with strong backwards compatibility guarantees. While the many users of Chisel across academia and industry show the success of this approach, there is a growing need for Chisel to move beyond its historical focus on designer productivity. The Chisel developers are taking a more holistic view of the design process to better capture the needs of other stakeholders including verification and physical design. To this end, we are introducing a new compiler built in CIRCT and a faster development process.
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