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Open tools for an open standard: Control/status register automation using SystemRDL
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Marks
Author(s):
Alex Mykyta
Location
UCSB Henley Hall room 1010
Date
apr Sat 01
Days Raw Files
Start
13:30
First Raw Start
12:57
Duration
00:20:00
Offset
0:32:01
End
13:50
Last Raw End
14:27
Chapters
00:00
0:19:19
0:21:03
Total cuts_time
25 min.
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We've all had the harrowing experience of hand-coding our register file RTL, manually updating the documentation, and then painstakingly transcribing it to software header files. What could possibly go wrong? If only we could automate this! Fortunately there is a growing ecosystem of highly-customizable open-source tools centered around SystemRDL - a register description design-entry language [published by Accellera](https://www.accellera.org/downloads/standards/systemrdl). SystemRDL lets you describe countless types of registers containing various access policies, counters, interrupts, and other commonly used CSR constructs. Using this language, you can build an information-rich single source of truth for all your register automation needs. This presentation will introduce a set of open-source tools developed specifically around SystemRDL. At the core is the [SystemRDL compiler front-end](https://systemrdl-compiler.readthedocs.io) that handles the RDL language processing and provides an intuitive Python API for register automation developers. Also featured is the toolchain called [PeakRDL](https://peakrdl.readthedocs.io), which uses this compiler to generate [various outputs](https://peakrdl.readthedocs.io/en/latest/gallery.html) such as rich HTML documentation, UVM register models, IP-XACT, as well as fully synthesizable SystemVerilog RTL. --- Alex is a principal FPGA/ASIC design engineer at SpaceX. This [collection of open-source SystemRDL tools](https://github.com/SystemRDL) started as a hobby project that "got slightly out of hand."
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