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Towards Cycle-accurate Simulation of xBGAS
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latch_2024
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Next: 10 Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture
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Author(s):
Jie Li
Location
b45r230
Date
apr Fri 19
Days Raw Files
Start
10:53
First Raw Start
10:24
Duration
00:20:00
Offset
0:29:17
End
11:13
Last Raw End
11:24
Chapters
00:00
0:00:42
Total cuts_time
18 min.
https://fossi-foundation.org/latch-up/2024
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High-performance computing (HPC) systems are evolving to address data-intensive workloads, shifting from monolithic architectures to integrated setups with microprocessors, accelerators, and advanced interconnects. However, this transition introduces complexities, latency challenges, and performance bottlenecks in large-scale parallel applications. To tackle these issues, the Extended Base Global Address Space (xBGAS) project enhances memory addressing through innovations in Instruction Set Architecture (ISA) and microarchitecture. Leveraging RISCV’s extensibility, xBGAS integrates an extended register file and new instructions, enabling efficient global memory access. In this presentation, we introduce REV-xBGAS, a cycle-based simulator using the Structural Simulation Toolkit (SST) to model xBGAS-enabled processors. With SST’s modularity, REV-xBGAS allows easy configuration of network latencies, bandwidths, and topologies, enabling performance evaluations under varied conditions.
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