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Name: BYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development
--client fossi --show latch_2024 --room b45r230 15381 --force
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Author(s):	Ajeetha Kumari Venkatesan
Location	b45r230
Date	apr Sat 20	Days Raw Files
Start	14:40	First Raw Start	13:24
Duration	00:20:00	Offset	1:15:37
End	15:00	Last Raw End	14:24
Chapters
Total cuts_time	None min.

https://fossi-foundation.org/latch-up/2024
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Description:	UVM is the most adopted design verification methodology in the field of ASIC and FPGA designs. Lint and static checking of code has proven to be very effective in projects that have a wide user base, longer lifetime, and distributed developers. During the recent UVM IEEE 1800.2-2023 release cycle, an observation was made regarding the potential application of a custom UVMLint solution to lint the UVM Base Class Library (BCL) as it gets developed, updated etc. We at AsFigo have developed custom rules for linting UVM BCL code on top of PySlint, an open-source SystemVerilog testbench linter. We intend to offer this as an opensource lint package to the UVM IEEE committee and to the general audience via public GitHub repository. The eventual goal is to have these rules as gatekeepers via GitHub actions so that any future code addition to the UVM BCL is free from common pitfalls. Based on early brainstorming, below are some of the sample lint rules that are relevant to the UVM BCL codebase: • Avoid race condition around "static const" (use localparam instead) • Avoid one-liner conditional statements: o if (cond) $display ("cond"); o if (cond) .. else $display ("Else cond as single line"); o case..endcase • Avoid one-liner code in loops: o for, repeat, while, do..while, foreach • Use enadlabels for elements such as endclass, endfunction, endtask etc. • Flag non-virtual methods Typical UVMLint rules for a VIP user would be quite different from the requirements of UVM BCL. These rules are tailored for UVM BCL codebase. As an example, a typical UVMLint rule for a VIP would be: • Check that agent is reusable by ensuring that active components are guarded with a conditional check to is_active == UVM_ACTIVE Such a rule is not quite useful for UVM BCL as it provides the base class library for tens of thousands of engineers around the globe using this library to build VIPs, verify their IPs, Systems etc. which ends up in your hardware using open-source initiatives. In this talk we show this cusotm approach for UVMLint development with sample Python code, tests, and results. A snapshot of UVMLint findings on latest IEEE 1800.2-2023 codebase using open source is below markdown
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