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Chisel 6 and beyond
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Next: 10 MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL
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Marks
Author(s):
Jack Koenig
Location
b45r230
Date
apr Fri 19
Days Raw Files
Start
13:00
First Raw Start
12:24
Duration
00:20:00
Offset
0:35:38
End
13:20
Last Raw End
13:54
Chapters
00:00
0:15:59
0:21:40
Total cuts_time
23 min.
https://fossi-foundation.org/latch-up/2024
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Chisel (formerly Chisel 3) is a hardware generator language embedded in the Scala general-purpose programming language. It empowers hardware designers to write reusable hardware generators to improve the productivity of design. At Latch Up last year, we discussed the new MLIR FIRRTL compiler and how that would enable more rapid feature development for Chisel. Today we are proud to discuss several of the new features of Chisel 6 and the coming Chisel 7 which improve verification and other non-design aspects of using the language.
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