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Name: Optimizing a new processor architecture
--client lca --show lca2017 --room plenary 12101 --force
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Author(s):	Rob Landley
Location	Plenary Hall
Date	jan Wed 18	Days Raw Files
Start	20:20	First Raw Start	20:05
Duration	0:45:0	Offset	0:14:56
End	21:05	Last Raw End	22:05
Chapters	00:00 0:14:32 0:44:32
Total cuts_time	48 min.

http://linux.conf.au/schedule/presentation/29/
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assets release.pdf Optimizing_a_new_processor_architecture.json
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When the last patents on the SuperH architecture started expiring in 2014, the http://j-core.org project released a new BSD-licensed clean room VHDL implementation of an SOC compatible with the sh2 instruction set already capable of booting Linux to a shell prompt on a $50 FPGA board. Linux Weekly news covered this at https://lwn.net/Articles/647636/

Now we'd like to talk about the things we've done to speed up linux, gcc, musl-libc, and the VHDL itself since we first got Linux booted on the thing ~3 years ago. We've doubled the MHZ, added SMP support, implemented futexes, ported everything to device tree, tracked down kernel and toolchain bugs of the "how did this ever work" variety (spoiler: it didn't), and even have a native compiler working on the board. We'll explain why we selected this architecture instead of i386/sparc/m68k (whose patents have had just as long to expire), scaling the processor design up to 64 bit and down to Arduino country at the same time, when the best way to go isn't clear because of tradeoffs (with a "prefetch vs cache" example), decisions about compatibility (sh2 vs sh3 system call numbers, should 64 bit mode have branch delay slots), issues with interrupts and clocks and futexes we hit modernizing an older architecture, and so on.

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