veyepar: Signal Analysis with Open Source Logic Analysers

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Name: Signal Analysis with Open Source Logic Analysers
--client lca --show lca2018 --room largepod 13545 --force
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Author(s):	Alastair D'Silva
Location	Large POD Room CB11.04.400
Date	jan Thu 25	Days Raw Files
Start	10:45	First Raw Start	10:36
Duration	0:100:0	Offset	0:08:33
End	12:25	Last Raw End	12:36
Chapters	00:00 0:02:13
Total cuts_time	4 min.

http://lca2018.linux.org.au/schedule/presentation/51/
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assets release.pdf Signal_Analysis_with_Open_Source_Logic_Analysers.json
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Description:	Hardware hacking often involves communicating with devices that do not have an existing library, or where the library does not implement features of the device that you require. The typical solution to this is that you grab the reference manual for the device, and develop software to achieve what you want. The question is, how do you debug your library when things go wrong? A key component of the debug process is looking at the signals going to the device and confirming that they are what you expect. This workshop provides the user with some basic hardware, and walks them through using the supplied logic analyser to debug a deliberately flawed library. Prerequisites: A basic understanding of C/C++. You won't need to write new code, but you should be able to understand and make changes to existing code. How to use a breadboard for electronic prototyping. If you haven't used a breadboard before, you can read up on how to use them on Adafruit, paying attention to how they are internally wired: https://learn.sparkfun.com/tutorials/how-to-use-a-breadboard An understanding of the 1Wire protocol. If you are not familiar with in, this tutorial provides a good description (flash required): https://www.maximintegrated.com/en/products/1-wire/flash/overview/ A laptop capable of running STLink and Pulseview. Setup instructions for both Windows and Linux are provided. Contributions for OSX are welcome. A minimum of 3 USB ports are required to complete this workshop easily, or 2 with a lot of port swapping. If your laptop has less than 3 available ports, a USB hub is strongly recommended. A $35 hardware kit is required to complete this workshop, which you can take home afterwards. It includes an ARM developer board, SWD programmer, 1wire device and logic analyser. A total of 50 kits are available. To reserve a seat in the workshop and a hardware kit, please add your name here: https://goo.gl/WGH2rz Attendees must have cloned the tutorial git repository and completed the included prerequisites before the start of the workshop: https://github.com/InfernoEmbedded/logicanalyser_workshop Objectives: - Program an ARM microcontroller using an SWD programmer - Read output from the microcontroller's serial port - Learn the basics of the 1Wire protocol - Use Sigrok to analyse the signal between the microcontroller and the device - Use Sigrok for higher level protocol analysis - Use Sigrok to debug device communications markdown
Comment:	production notes

2018-01-25/10_36_27.ts Apply: 10:45:33 - 10:47:47 ( 00:02:13 ) S: 10:36:27 - E: 11:06:27 D: 00:30:00 (Start: 546.993916) (End: 680.0) show more...

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2018-01-25/10_36_27.ts Apply: 10:47:47 - 10:49:37 ( 00:01:50 ) S: 10:36:27 - E: 11:06:27 D: 00:30:00 (Start: 680.0) (End: 790.0) show more...

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2018-01-25/10_36_27.ts Apply: 10:49:37 - 11:06:27 ( 00:16:50 ) S: 10:36:27 - E: 11:06:27 D: 00:30:00 (Start: 790.0) show more...

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2018-01-25/11_06_27.ts Apply: 11:06:27 - 11:36:27 ( 00:30:00 ) S: 11:06:27 - E: 11:36:27 D: 00:30:00 show more...

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2018-01-25/11_36_27.ts Apply: 11:36:27 - 12:06:26 ( 00:29:59 ) S: 11:36:27 - E: 12:06:26 D: 00:29:59 show more...

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2018-01-25/12_06_27.ts Apply: 12:06:27 - 12:36:27 ( 00:30:00 ) S: 12:06:27 - E: 12:36:27 D: 00:30:00 show more...

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