veyepar: DUH: document and tools for HW design reuse

Author(s):	Aliaksei Chapyzhenka
Location	Revolution Hall
Date	may Sun 05	Days Raw Files
Start	13:50	First Raw Start	15:28
Duration	0:30:0	Offset	1:38:32
End	14:20	Last Raw End	16:28
Chapters	00:00 0:20:36
Total cuts_time	24 min.

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SoC integration is a complex process requiring integration of multiple design components together. Typical “reusable” Soft / Hard core component
                comes with the intricate integration story hopefully described in some human readable User Guide document. Connecting all ports, parameters,
                registers, bus interfaces, clocks, resets, sideband signals, etc. becoming a very tedious, error prone process. Multiple attempts were made
                to introduce some sort of standard metadata exchange format to express this integration intent. Most of these formats are proprietary or EDA
                vendor specific and are semi-useful in the world of open source silicon tools.
              
                DUH defines a JSON5-based document format and provides a suite of tools for handling reusable hardware components. Import tools allow extraction
                of ports, parameters, and other important integration information from available sources like Verilog, IP-XACT, SystemRDL, etc. Inference tools
                helps to reason about structure of the ports, standard bus interfaces, clocks, resets. Validation tools helps document author to maintain complete
                and consistent DUH document describing specific hardware component. Integration tools can read DUH documents to understand and satisfy an integration
                needs of these components.

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