pre-release: Fossi Foundation meeting announcement

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Subject: 
ANN: Fossi Foundation at Revolution Hall Sat May 4, 9p


Fossi Foundation
=========================
When: 9 AM Saturday May 4, 2019
Where: Revolution Hall

https://fossi-foundation.org/latchup/

Topics
------
1. Welcome


(Needs description.) 
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2. FOSSi Foundation Update


(Needs description.) 
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3. Diagrams and system visualisation in chip design
Aliaksei Chapyzhenka


                Chip designers use multiple forms of illustrations to present information of technical nature quickly and clearly. Illustrations
                employed to mobilize human visual system ability to recognize trends, patterns and differences. Some forms of illustrations are
                universally accepted. Data tables, plots, line charts, mechanical drawings can be used to communicate information to the general public.
                Specialized diagram types (like UML) can be reused from software or system design practice. Such diagrams are capable of describing
                complex structure or behavior and convey this information to the broad science and engineering community.
              
                Like any other specific field of science / engineering -- chip designers developed own specialized visual language to communicate
                complex ideas with clarity, precision and efficiency. Schematic symbols; timing, circuit, layout diagrams were originally developed
                for paper medium, now migrated into electronic documentation. Many design tools exists to create illustrations and diagrams.
                From generic to specialized. Some require freehand drawing skills, some perform automatic layout.
              
                This talk is about ideas, principles and tools that would help you to create good diagrams.
	      
 recording release: yes license: CC-BY  

4. Netlistsvg: How to Draw a Better Schematic than Graphviz
Neil Turley


                Taking a description of components and the connections between them and converting it into a reasonable
                looking image is a surprisingly complicated problem. Digital netlist visualization is useful for pedagogy,
                documentation, and debugging and is commonly integrated into proprietary FPGA toolchains such as Vivado
                or Quartus. Netlistsvg is a simple
                tool that takes yosys netlists in JSON format, and attempts to create an easily understandable image in
                SVG format.
	      
 recording release: yes license: CC-BY  

5. Lessons learned customising the Rocket RISC-V core
Julius Baxter


                This presentation will cover Morse Micro's adaptation of the
                Berkeley/SiFive Rocket chip generator in developing single-chip 802.11ah solutions. We will discuss the pros and
                cons of Chisel, Rocket's architecture, and aspects of our work in taking the Rocket project and implementing
                multiple deeply-embedded-class micro-controllers.
	      
 recording release: yes license: CC-BY  

6. Higher-Order Hardware Design with Chisel 3
Jack Koenig


Chisel 3 is a hardware construction language embedded in Scala that enables
                digital designers to write parameterized generators using object-oriented and functional programming abstractions. The power of
                Chisel is not the language itself, but rather the abstractions one can create to make hardware design more productive, more reusable,
                and less error-prone. Sophisticated hardware generators like Rocket-Chip, BOOM, Hwacha, and even the Google Edge TPU are implemented using Chisel.
              
 recording release: yes license: CC-BY  

7. The fusion of high-level synthesis with event-oriented hardware description (myhdl)
Christopher Felton


                Many of the high-level synthesis (HLS) approaches take existing procedural programming languages, such as the
                C programming language, and add extensions to the language (e.g. pragmas) to accommodate high-level synthesis.
                An alternate approach is to use the myhdl design patterns to
                describe HLS chunks and integrate them with existing
                event-oriented (simulation-oriented, a.k.a RTL) hardware description languages (HDL).  This approach allows a
                designer to seamlessly move between HDL and HLS levels of abstractions and use both descriptions in a single
                programming environment.
              
 recording release: yes license: CC-BY  

8. JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor
Katie Lim


                Heterogeneous-ISA processors have become a topic of research interest due to the increasing need for energy efficiency.
                Without a fully open-source implementation of a heterogeneous-ISA processor, it is difficult to test full-stack modifications.
                By connecting PicoRV32 to the
                OpenPiton cache system, we created
                JuxtaPiton,
                a heterogeneous-ISA platform with both OpenPiton’s original OpenSPARC T1 cores and PicoRV32 cores.
              
 recording release: yes license: CC-BY  

9. OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh
Jonathan Balkind


                You may have heard of Ariane from ETH Zurich,
                or of OpenPiton from Princeton University, but now from the makers
                of both, comes
                OpenPiton+Ariane!
              
 recording release: no  

10. Lessons Learned from Open-Sourcing NVDLA
Joshua Wise


                In 2017, NVIDIA released their formerly-proprietary "NVDLA" deep learning accelerator IP as open source hardware.
                The process of transitioning from a closed IP model, backed by all the tooling available at a large company, to a
                community-available IP with the intent of being built "outside the walls" of NVIDIA, was unsurprisingly challenging,
                and the logistics of packaging hardware up for outside distribution modification was more difficult than we had
                originally anticipated.
              
                In this discussion, I will talk some about things that went well, and things that I wish we
                had been prepared for at the start; additionally, I'll provide some tips and tricks for other organizations that may be
                interested in releasing their own IP as open source.
	      
 recording release: no  

11. DVKit: An Integrated Development Environment for Design and Verification Engineers
Matthew Ballance


                Design and Verification engineers develop code using a plethora of languages -- Verilog, SystemVerilog, C/C++, Python, Perl, etc.
                Whether developing commercial or open source IP, reuse is critical, which means that DV engineers need to efficiently
                comprehend and work with code written by others. DVKit is an Eclipse-based
                Integrated Development Environment (IDE) that supports developing in a wide variety of software and hardware description
                languages much more efficiently than can be done with a text editor.
              
 recording release: yes license: CC-BY  

12. Live Graph infrastructure for Synthesis and Simulation
Jose Renau


LGraph
                is compiler infrastructure to support hardware languages.
		The goal is to become the LLVM of hardware. LGraph is a graph
		optimized for live synthesis and simulation (Live Synthesizes
		Graph or LGraph for short). By live, we mean that small changes
		in the design should have results in few seconds. The goal is
		that any code change can have its synthesis and simulation setup
		ready under 30 seconds with a goal of under 4 seconds in most cases.
	      
 recording release: yes license: CC-BY  

13. The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor
Jerry Zhao, Abe Gonzalez, Ben Korpan


                We present BOOM, the Berkeley Out-of-Order Machine, a synthesizable and
                parameterizable open source RV64GC RISC-V processor written in the Chisel hardware construction language. BOOM is able to
                run Linux, Fedora, and other workloads both in the cloud using the FireSim FPGA simulation platform and on a taped-out academic
                chip. For researchers, BOOM serves as a highly productive platform for implementing and evaluating new high performance designs
                and accelerators.
              
 recording release: yes license: CC-BY  

14. FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud
David Biancolin, Alon Amid


                We present FireSim , an easy-to-use, open-source, FPGA-accelerated
                cycle-accurate hardware simulation platform that runs on Amazon EC2 F1. FireSim automatically transforms and
                instruments open-hardware designs (e.g. RISC-V
                Rocket Chip,
                BOOM,
                Hwacha,
                NVDLA, etc.) with the MIDAS framework
                into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification
                and performance validation.
              
 recording release: yes license: CC-BY  

15. How I started learning FPGA: My journey writing a GameBoy in Verilog
Wenting Zhang


                Coding can be fun, there are many people coding in their free time just for fun. FPGA's unique features and capabilities makes it
                an attractive target for enthusiasms. VerilogBoy is such an FPGA project, that is built simply for fun. The
                VerilogBoy project consists of two parts. The first part is
                implementing a GameBoy compatible machine in Verilog. The second part is building an FPGA-based handheld game console.
              
 recording release: yes license: CC-BY  

16. Emulation of vintage integrated circuits through die analysis and reverse-EDA
Cole Johnson


                Despite being sold in the millions, video games based on discrete game ICs have had minimal emulation developed.
                This is primarily due to the circuitry being a literal "black box" as only the manufacturer possessed the designs.
                In addition, much of the documentation surrounding these games has disappeared over the years.
              
                Cole has been developing a process to re-implement these stubborn circuits in modern FPGAs as well as software.
                It involves extracting a transistor-level netlist from high-resolution photographs of the exposed silicon die.
                Reverse-engineering and slow simulation is achieved using tools pioneered by the visual6502 project. This is followed
                by reverse-EDA performed by custom tools being developed. The transistor-level design is automatically converted into
                a more abstract RTL circuit description.
              
                Verilog obtained from the above process will be ported to the tinyFPGA board, the
                MiSTer hardware emulation project,
                and the MAME software emulator. The intermediate files will be open-source in the spirit of the target projects.
	      
 recording release: yes license: CC-BY  

17. Mingle, drinks


(Needs description.) 
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18. BaseJump STL: a Standard Template Library for Hardware Design
Daniel Petrisko


                SystemVerilog is widely used for hardware design in both academia and industry.
                BaseJump STL is an open-source Standard Template Library
                for synthesizable SystemVerilog that sharply reduces the time required to design
                digital circuits. This talk will overview the principles that underly the design
                of the BaseJump STL, including light-weight latency-insensitive interfaces that yield fast microarchitectures and low bug
                density; thin handshaking rules; fast porting of hardened chip regions across nodes; pervasive parameterization and specialization,
                and static error checking.
              
 recording release: yes license: CC-BY  

19. OSVVM, VHDL's #1 FPGA Verification Library
Jim Lewis


		Open Source VHDL Verification Methodology (OSVVM) is an ASIC
		level VHDL verification methodology that is simple enough to use
		even on small FPGA projects. OSVVM offers the same capabilities
		as other verification languages such as SystemVerilog and UVM.
	      
		This presentation provides an overview of OSVVM's capabilities, including:
		Transaction-Based Modeling
Constrained Random test generation
Functional Coverage with hooks for UCIS coverage database integration
Intelligent Coverage Random test generation
Utilities for testbench process synchronization
Transcript files
Error logging and reporting – Alerts and Affirmations
Message filtering – Logs
Scoreboards and FIFOs (data structures for verification)
Memory models

 recording release: yes license: CC-BY  

20. Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
Matthew Ballance


		Open source and industry have a long history of overlapping in the software space. Engineers from industry often
		work on open-source software in their free time, open source software is used in commercial applications, and
		students use open-source software to learn about how real software is designed, developed, and tested. A key
		enabler is that open-source software is largely developed and tested in the same way that commercial software is.
		Commercial software development often uses commercial tools with features beyond what is available to open-source
		developers, but the large degree to which techniques and methodologies are aligned facilitates collaboration.
	      
		What of open source silicon? We certainly use standard design languages (Verilog and VHDL). But verification in
		the industry is typically done with SystemVerilog and UVM, and SystemVerilog tools are out-of-reach for the
		open-source silicon developer. Or, are they? As it turns out, there are both open-source and freely-available
		tools, and educational resources, to help open-source silicon developers create verification environments that
		align with commercial verification practices. This talk will present tools and educational resources for creating
		SystemVerilog and UVM testbench environments, as well as techniques for creating SystemVerilog and UVM testbenches
		for open-source silicon that both work with freely-available tools and scale to take advantage of the features of
		commercial simulation tools.
	      
 recording release: yes license: CC-BY  

21. RISC-V in Debian
Vagrant Cascadian

Debian's port for 64-bit RISC-V, riscv64, already builds
                88% of Debian's available packages. It's possible to build a
                foreign-architecture chroot with qemu, or a fully virtualized riscv64 system. What are the remaining blockers to
                include riscv64 in a Debian release?
 recording release: yes license: CC-BY  

22.  Lightning Talks 


(Needs description.) 
 recording release: no  

23. Hermes-Lite: Amateur Radio SDR
Steve Haynal
tags: SDR
The Hermes-Lite is a low-cost direct down/up conversion software defined amateur radio HF transceiver based on a broadband modem chip and the Hermes SDR project. It is entirely open source and open hardware, including the tools used for design and fabrication files. Over 100 Hermes-Lite 2.0 units have been successfully built.
 recording release: yes license: CC BY-SA  

24. Tim has too many projects - LatchUp Edition
Tim 'mithro' Ansell
tags: fpga SymbiFlow Migen
Tim has too many projects and needs your help or he may never sleep again! Find out how this Australian started trying to record conferences with the TimVideo project, developed custom FPGA based HDMI capture hardware with the HDMI2USB.tv project, ended up using the Python based HDL system called Migen & LiteX and why it made the project possible. Finally hear about the SymbiFlow project and Tomu FPGA as he tries to get software developers involved in his projects.
 recording release: yes license: CC BY-SA  

25. FuseSoC - Cores have never been so much fun
Olof Kindgren


                In many ways, HDL developers have been many years behind their counterparts in the software world.
                One such area is core management. Where the software developers simply specify which libraries they
                depend on, HDL developers rely on copying around source code. Where software developers can select
                their build tool with a flick of a switch, HDL developers use tool-specific project files powered by
                custom makefiles.
              
FuseSoC rectifies this by bringing a modern
                package manager and a uniform build system to HDL developers, making it easy to reuse existing code,
                change tools and move projects between FPGAs from different vendors. Having been around for seven years
                there are now hundreds of FuseSoC-compatible cores and 14 different simulation, synthesis and lint tools
                supported. This presentation will give an overview of where FuseSoC can help spending less time on the
                cores, and more time on the core business    
	      
 recording release: yes license: CC-BY  

26. DUH: document and tools for HW design reuse
Aliaksei Chapyzhenka


                SoC integration is a complex process requiring integration of multiple design components together. Typical “reusable” Soft / Hard core component
                comes with the intricate integration story hopefully described in some human readable User Guide document. Connecting all ports, parameters,
                registers, bus interfaces, clocks, resets, sideband signals, etc. becoming a very tedious, error prone process. Multiple attempts were made
                to introduce some sort of standard metadata exchange format to express this integration intent. Most of these formats are proprietary or EDA
                vendor specific and are semi-useful in the world of open source silicon tools.
              
                DUH defines a JSON5-based document format and provides a suite of tools for handling reusable hardware components. Import tools allow extraction
                of ports, parameters, and other important integration information from available sources like Verilog, IP-XACT, SystemRDL, etc. Inference tools
                helps to reason about structure of the ports, standard bus interfaces, clocks, resets. Validation tools helps document author to maintain complete
                and consistent DUH document describing specific hardware component. Integration tools can read DUH documents to understand and satisfy an integration
                needs of these components.
	      
 recording release: yes license: CC-BY  

27. Nyuzi: An Open Source GPGPU Processor
Jeff Bush


Nyuzi began as a way to explore tradeoffs
                between general purpose and fixed function hardware. This presentation will talk about the original goals of the project,
                the process of building a new microarchitecture, and some learnings from it.
	      
 recording release: yes license: CC-BY  

28. OpenRAM: An Open Source Memory Compiler
Matthew Guthaus

OpenRAM is an open-source Python framework
                to create the layout, netlists, timing and power models, placement and routing models, and other views necessary
                to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both
                predictive and fabricable technology.
 recording release: yes license: CC-BY  

29. SYZYGY: An Open Standard For Semiconductor Evaluation
Tom McLeod

So you've designed and built an amazing new piece of silicon. No doubt customers are lining up to try
		it out, but how do you go about providing an evaluation platform for them?
	      
SYZYGY provides the answer with an open standard
		for high performance connectivity to an FPGA.
		SYZYGY was designed to economize FPGA pin usage without compromising per-pin performance. Built with a focus
		on FPGA-specific requirements, SYZYGY fits comfortably between Digilent Pmod and VITA-57 FMC standards.
		Developing a SYZYGY-based evaluation peripheral opens up support for numerous host platforms as well as
		easier integration into your customer's product. This presentation will provide an overview on the SYZYGY
		standard, why it's needed, and what it offers.
 recording release: yes license: CC-BY  

30. Open-Source FPGA tools, how and why?
Piotr Esden-Tempski

In this talk Piotr presents the OpenSource FPGA tool stack. Which devices are currently supported and which
                ones are being worked on. Also he talks about how these tools revived his interest in FPGA in general, and
                why they are important.
 recording release: yes license: CC-BY  



Location
--------
Revolution Hall


About the group
---------------
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon.

Latch-Up: a weekend of presentations and networking for the open source silicon community, much like its European sister conference ORConf.