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Loc: #574 Revolution Hall
id seq startend duration state episode.name episode.authors released
14798 0 Sat 04 09:00 09:10 0:10:0 8 Welcome False Y
14799 1 Sat 04 09:10 09:30 0:20:0 8 FOSSi Foundation Update False Y
14800 2 Sat 04 09:30 10:00 0:30:0 12 Diagrams and system visualisation in chip design Aliaksei Chapyzhenka True Y
14801 3 Sat 04 10:00 10:30 0:30:0 8 Netlistsvg: How to Draw a Better Schematic than Graphviz Neil Turley True Y
14802 4 Sat 04 10:50 11:10 0:20:0 12 Lessons learned customising the Rocket RISC-V core Julius Baxter True Y
14803 5 Sat 04 11:10 11:40 0:30:0 8 Higher-Order Hardware Design with Chisel 3 Jack Koenig True Y
14804 6 Sat 04 11:40 12:10 0:30:0 8 The fusion of high-level synthesis with event-oriented hardware description (myhdl) Christopher Felton True Y
14805 7 Sat 04 13:30 13:50 0:20:0 8 JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor Katie Lim True Y
14806 8 Sat 04 13:50 14:10 0:20:0 8 OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh Jonathan Balkind False Y
14807 9 Sat 04 14:10 14:30 0:20:0 8 Lessons Learned from Open-Sourcing NVDLA Joshua Wise False Y
14808 10 Sat 04 14:30 14:50 0:20:0 8 DVKit: An Integrated Development Environment for Design and Verification Engineers Matthew Ballance True Y
14809 11 Sat 04 15:30 16:00 0:30:0 12 Live Graph infrastructure for Synthesis and Simulation Jose Renau True Y
14810 12 Sat 04 16:00 16:30 0:30:0 8 The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor Jerry Zhao, Abe Gonzalez, Ben Korpan True Y
14811 13 Sat 04 16:30 17:00 0:30:0 8 FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud David Biancolin, Alon Amid True Y
14812 14 Sat 04 17:30 18:00 0:30:0 12 How I started learning FPGA: My journey writing a GameBoy in Verilog Wenting Zhang True Y
14813 15 Sat 04 18:00 18:30 0:30:0 12 Emulation of vintage integrated circuits through die analysis and reverse-EDA Cole Johnson True Y
14814 16 Sat 04 18:20 18:50 0:30:0 0 Mingle, drinks False
14815 17 Sun 05 09:30 10:00 0:30:0 8 BaseJump STL: a Standard Template Library for Hardware Design Daniel Petrisko True Y
14816 18 Sun 05 10:00 10:30 0:30:0 12 OSVVM, VHDL's #1 FPGA Verification Library Jim Lewis True Y
14817 19 Sun 05 10:30 11:00 0:30:0 8 Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor Matthew Ballance True Y
14818 20 Sun 05 11:20 11:40 0:20:0 12 RISC-V in Debian Vagrant Cascadian True Y
14819 21 Sun 05 11:40 12:10 0:30:0 0 Lightning Talks False
14826 28 Sun 05 11:49 12:01 00:12:00 12 Hermes-Lite: Amateur Radio SDR Steve Haynal True Y
14827 28 Sun 05 12:01 12:29 00:28:00 12 Tim has too many projects - LatchUp Edition Tim 'mithro' Ansell True Y
14820 22 Sun 05 13:20 13:50 0:30:0 12 FuseSoC - Cores have never been so much fun Olof Kindgren True Y
14821 23 Sun 05 13:50 14:20 0:30:0 12 DUH: document and tools for HW design reuse Aliaksei Chapyzhenka True Y
14822 24 Sun 05 14:20 14:50 0:30:0 12 Nyuzi: An Open Source GPGPU Processor Jeff Bush True Y
14823 25 Sun 05 15:10 15:40 0:30:0 12 OpenRAM: An Open Source Memory Compiler Matthew Guthaus True Y
14824 26 Sun 05 15:40 16:10 0:30:0 0 SYZYGY: An Open Standard For Semiconductor Evaluation Tom McLeod True
14825 27 Sun 05 16:00 16:20 0:20:0 12 Open-Source FPGA tools, how and why? Piotr Esden-Tempski True Y

Veyepar Video Eyeball Processor and Review