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Loc: #612 B7141
id seq startend duration state episode.name episode.authors released
15514 17 Thu 15 09:00 09:10 10:00 1 https://meza.wiki/mwplus/MediaWiki_Users_and_Developers_Workshop_Spring_2025/From_Hooks_to_Events:_evolving_MediaWiki%27s_extension_interfaces None
Loc: #589 UCSB Henley Hall room 1010
id seq startend duration state episode.name episode.authors released
15222 0 Fri 31 13:30 13:50 00:20:00 10 FireSim: A Scalable Platform for FPGA-Accelerated Simulation, Debugging, Profiling of RTL Designs Sagar Karandikar True Y
15223 1 Fri 31 14:00 14:20 00:20:00 10 bsg_tag: A minimal open-source ASIC configuration bus Dan Petrisko True Y
15224 2 Fri 31 15:00 15:20 00:20:00 10 OmniXtend: coherent scaleout over commodity fabrics Dejan Vucinic True Y
15225 3 Fri 31 15:30 15:50 00:20:00 10 Hammer: A Modular and Reusable Physical Design Flow Tool Nayiri Krzysztofowicz True Y
15226 4 Fri 31 16:00 16:20 00:20:00 10 CIRCT: Open Source Circuit IR Compilers and Tools Mike Urbach True Y
15227 5 Fri 31 17:00 17:20 00:20:00 10 Accelerating Chisel Development Jack Koenig True Y
15228 6 Fri 31 17:30 17:50 00:20:00 10 Open-Source HW Commercial Adoption Rick O'Connor True Y
15229 7 Sat 01 08:30 08:50 00:20:00 10 A UCSC Professor's path through Open-Source Hardware Jose Renau True Y
15230 8 Sat 01 08:55 09:15 00:20:00 0 So You Want to be an Open Sourcerer? Dustin Richmond True
15232 0 Sat 01 08:55 09:15 00:20:00 10 If You Build It, Who Will Come? Scott Beamer True Y
15233 1 Sat 01 09:20 09:40 00:20:00 10 Yet Another UCSC Professor’s path through Open-Source Hardware Matt Guthaus True Y
15234 2 Sat 01 09:45 10:05 00:20:00 10 Tapeout-in-a-Semester: The Organization of Berkeley's Tapeout Course Jerry Zhao True Y
15254 22 Sat 01 10:10 10:30 00:20:00 10 Fearless Hardware Design Rachit Nigam True Y
15235 3 Sat 01 11:00 11:20 00:20:00 10 Minimax - a Compressed-First, Microcoded RISC-V CPU Graeme Smecher True Y
15236 4 Sat 01 11:30 11:50 00:20:00 10 Open Source Brain-Inspired Neuromorphic Software and Hardware Jason Eshraghian True Y
15255 0 Sat 01 12:57 13:00 00:3:00 10 Gdsfactory, an Open Source python flow for circuit design, verification and validation Joaquin Matres True Y
15237 5 Sat 01 13:00 13:03 00:3:00 10 RISu064 - An in-order non-blocking dual-issue RISC-V 64 processor Wenting Zhang True Y
15238 6 Sat 01 13:03 13:06 00:3:00 10 SimCommand: A High-Performance RTL Testbench API with Fork/Join Support Vighnesh Iyer True Y
15239 7 Sat 01 13:06 13:09 00:3:00 10 A radically simple 1-bit single-die "supercomputer" James Bowman True Y
15240 8 Sat 01 13:09 13:12 00:3:00 10 All Your OSS Codebase Are Belong To Us Oron Port True Y
15241 9 Sat 01 13:12 13:15 00:3:00 10 A Modular Approach to Variable Pipeline Depth Designs Peter Herrmann True Y
15242 10 Sat 01 13:15 13:18 00:3:00 10 Open-source Hardware for Real-Time Applications Francisco Wilken True Y
15243 11 Sat 01 13:18 13:21 00:3:00 10 An open-source robotics applications interface Nikita Klimov True Y
15256 1 Sat 01 13:21 13:24 00:3:00 10 DSAGEN: Democratizing Domain-Specific Accelerator Generation for FPGA Overlays Dylan Kupsh True Y
15257 2 Sat 01 13:24 13:27 00:3:00 10 Educational Framework for Functional Verification Matthew Michilot True Y
15258 3 Sat 01 13:27 13:30 00:3:00 10 Using CVA6 in Architecture Education Ethan Sifferman True Y
15244 12 Sat 01 13:30 13:50 00:20:00 4 Open tools for an open standard: Control/status register automation using SystemRDL Alex Mykyta False
15245 13 Sat 01 14:00 14:20 00:20:00 10 Goodbye Make, Hello SiliconCompiler! Andreas Olofsson True Y
15246 14 Sat 01 15:00 15:20 00:20:00 10 Chipyard: An Open-Source RISC-V SoC Design Framework Abraham Gonzalez True Y
15247 15 Sat 01 15:30 15:50 00:20:00 10 SVA based Checker IP in Verilator Balram, Srinivasan Venkataramanan True Y
15248 16 Sat 01 16:00 16:20 00:20:00 10 Quality of Life with Virtual Prototypes - Open Source Tools in the Ecosystem of the RISC-V VP Pascal Pieper True Y
15249 17 Sun 02 09:00 09:20 00:20:00 10 Constellation: A Open-Source Chisel Generator for Network-on-Chip Interconnects Jerry Zhao True Y
15250 18 Sun 02 09:30 09:50 00:20:00 10 SystemVerilog-Style Constraints and Functional Coverage in Python Matthew Ballance True Y
15251 19 Sun 02 10:00 10:20 00:20:00 10 OpenROAD - Turning Designs into Optimized Silicon Matt Liberty True Y
15253 21 Sun 02 11:00 11:20 00:20:00 10 Space - Opportunities, Challenges for Open Source Community CHINH LE True Y
15252 20 Sun 02 11:00 11:20 00:20:00 10 Online Waveform viewer. Why do we need one? Aliaksei Chapyzhenka True Y

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