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Revolution Hall
Sat 04
09:00 [_] Welcome
09:10 [_] FOSSi Foundation Update
09:30 [_] Diagrams and system visualisation in chip design
10:00 [_] Netlistsvg: How to Draw a Better Schematic than Graphviz
10:50 [_] Lessons learned customising the Rocket RISC-V core
11:10 [_] Higher-Order Hardware Design with Chisel 3
11:40 [_] The fusion of high-level synthesis with event-oriented hardware description (myhdl)
01:30 [_] JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor
01:50 [_] OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh
02:10 [_] Lessons Learned from Open-Sourcing NVDLA
02:30 [_] DVKit: An Integrated Development Environment for Design and Verification Engineers
03:30 [_] Live Graph infrastructure for Synthesis and Simulation
04:00 [_] The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor
04:30 [_] FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud
05:30 [_] How I started learning FPGA: My journey writing a GameBoy in Verilog
06:00 [_] Emulation of vintage integrated circuits through die analysis and reverse-EDA
06:20 [_] Mingle, drinks
Revolution Hall
Sun 05
09:30 [_] BaseJump STL: a Standard Template Library for Hardware Design
10:00 [_] OSVVM, VHDL's #1 FPGA Verification Library
10:30 [_] Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
11:20 [_] RISC-V in Debian
11:40 [_] Lightning Talks
11:49 [_] Hermes-Lite: Amateur Radio SDR
12:01 [_] Tim has too many projects - LatchUp Edition
01:20 [_] FuseSoC - Cores have never been so much fun
01:50 [_] DUH: document and tools for HW design reuse
02:20 [_] Nyuzi: An Open Source GPGPU Processor
03:10 [_] OpenRAM: An Open Source Memory Compiler
03:40 [_] SYZYGY: An Open Standard For Semiconductor Evaluation
04:00 [_] Open-Source FPGA tools, how and why?

Veyepar Video Eyeball Processor and Review