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Minimax - a Compressed-First, Microcoded RISC-V CPU
--client
fossi
--show
latch_2023
--room henley1010 15235 --force
Next: 10 Open Source Brain-Inspired Neuromorphic Software and Hardware
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Marks
Author(s):
Graeme Smecher
Location
UCSB Henley Hall room 1010
Date
apr Sat 01
Days Raw Files
Start
11:00
First Raw Start
10:07
Duration
00:20:00
Offset
0:52:34
End
11:20
Last Raw End
12:07
Chapters
00:00
0:06:12
0:22:40
Total cuts_time
32 min.
https://www.fossi-foundation.org/latchup/#presentations
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RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular instruction set. Thought experiment: can a RISC-V CPU directly execute only the RVC instructions, and emulate the uncompressed instruction set in microcode? The result is Minimax: the smallest¹, fastest² RV32IC core available - with the weasel words hidden in the fine print. In this presentation, I will show how Minimax fits in with the other excellent open-source RISC-V cores already available.
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