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Name: Chipyard: An Open-Source RISC-V SoC Design Framework
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Author(s):	Abraham Gonzalez
Location	UCSB Henley Hall room 1010
Date	apr Sat 01	Days Raw Files
Start	15:00	First Raw Start	14:27
Duration	00:20:00	Offset	0:32:01
End	15:20	Last Raw End	15:57
Chapters	00:00 0:19:28
Total cuts_time	31 min.

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Description:	We present Chipyard - an open-source integrated system-on-chip (SoC) design, simulation, and implementation environment for specialized RISC-V compute systems. Chipyard includes parameterized, composable, open-source, generator-based IP blocks that can be used across multiple stages of the hardware development flow while maintaining design intent and integration consistency. Through FPGA simulation and rapid ASIC implementation, this framework allows for continuous validation of physically realizable customized systems. Through integration with the Rocket Chip generator ecosystem, Chipyard provides a large number of easily composable and extensible open-source digital IP blocks including Linux-capable cores, accelerators, and system components. Chipyard contains mainstream energy-efficient and high-performance processor cores (Rocket, SonicBOOM, CVA6, Ibex, Sodor), domain specific accelerators (Hwacha/Gemmini/NVDLA vector/ML, SHA3/FFT/Mempress misc.), memory systems (caches, scratchpads, DRAMSim2), on-chip interconnects (Constellation) and additional peripherals to help create a fully featured SoC. Chipyard enables customization through intra-core and inter-core configuration, as well as custom extensions using the Rocket Custom Co-processor (RoCC) interface and MMIO-based devices. Chipyard also allows users to seamlessly integrate their own SystemVerilog custom IPs. Additionally, Chipyard provides software workload management tooling (FireMarshal) and toolchains for users to generate custom baremetal and Linux-based workloads for generated custom SoCs. As the SoC is co-designed for a specific use case, Chipyard enables pushing the entire SoC through automated ASIC flows (e.g. Hammer), software simulation (e.g. Verilator), FPGA prototyping flows (e.g. Vivado), and FPGA-accelerated simulation flows (e.g. FireSim). This allows the user to measure their workloads of interest in a fully automated way. Harnessing the integration with the Hammer ASIC physical design framework, users can run power-analysis simulation, go from gates to a GDSII, and more, in a minimal amount of time in both commercial and open-source process technologies (SKY130) and tooling (OpenRoad). For pre-silicon simulation and prototyping, users can use Verilator or FPGA prototyping for quick design/test cycle. For even faster continuous and simultaneous development for higher-quality verification and validation, users can use the FireSim FPGA-accelerated simulation platform for additional scale, accuracy, and debuggability. In this talk, we cover how the open-source Chipyard “one-stop shop” SoC framework enables users to create, integrate, test, and measure their own hardware designs. To date Chipyard has enabled end-to-end computer architecture research and development in over 15 academic and industrial institutions across all domains. markdown
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