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Name: SVA based Checker IP in Verilator
--client fossi --show latch_2023 --room henley1010 15247 --force
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Author(s):	Balram, Srinivasan Venkataramanan
Location	UCSB Henley Hall room 1010
Date	apr Sat 01	Days Raw Files
Start	15:30	First Raw Start	14:57
Duration	00:20:00	Offset	0:32:01
End	15:50	Last Raw End	16:27
Chapters	00:00 0:13:48 0:17:00
Total cuts_time	18 min.

https://www.fossi-foundation.org/latchup/#presentations
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Checkers are a critical part of the design verification process. With the advent of constrained-random techniques, a lot of stimulus-generation capabilities are supported by languages, methodologies, and supporting tools. Ensuring that a design behaves as per the specification is achieved using various forms of checkers. The term “checker” at times means different things to different people. With SystemVerilog 2009 standard making “checker” as a keyword in the language itself, we would like to use that for temporal checks using assertions. Verilator is a free and open-source simulator that can convert SystemVerilog code into a cycle-accurate executable model. Assertions are statements that specify properties or constraints that the design should satisfy. In this paper, we present our experience in porting some of our Checker IPs (APB, AHB, etc.) developed and used in production to Verilator. Given the SVA support is still maturing in Verilator, our team had to adapt the code to be restricted to what the tool supports. We also developed unit tests to verify these properties in Verilator. We will share our findings, potential areas to improve, etc. Our intention is to make this code base available as part of GO2UVM library.

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2023-04-01/14_57_59.ts Apply: 14:57:59 - 15:08:30 ( 00:10:31 ) S: 14:57:59 - E: 15:27:58 D: 00:29:59 (End: 631.0) show more...

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2023-04-01/15_27_59.ts Apply: 15:40:50 - 15:40:58 ( 00:00:08 ) S: 15:27:59 - E: 15:57:58 D: 00:29:59 (Start: 771.0) (End: 779.0) show more...

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2023-04-01/15_27_59.ts Apply: 15:40:58 - 15:54:46 ( 00:13:48 ) S: 15:27:59 - E: 15:57:58 D: 00:29:59 (Start: 779.0) (End: 1607.0) show more...

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2023-04-01/15_57_59.ts Apply: 15:59:12 - 15:59:52 ( 00:00:40 ) S: 15:57:59 - E: 16:27:59 D: 00:30:00 (Start: 73.0) (End: 113.0) show more...

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2023-04-01/15_57_59.ts Apply: 15:59:52 - 16:20:07 ( 00:20:15 ) S: 15:57:59 - E: 16:27:59 D: 00:30:00 (Start: 113.0) (End: 1328.0) show more...

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