veyepar: Switchboard: Calling All Hardware Models

Author(s):	Steven Herbst
Location	b45r230
Date	apr Sat 20	Days Raw Files
Start	11:00	First Raw Start	09:26
Duration	00:20:00	Offset	1:33:06
End	11:20	Last Raw End	10:26
Chapters	00:00 0:14:27
Total cuts_time	16 min.

https://fossi-foundation.org/latch-up/2024
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Switchboard is a high-performance and easy-to-use tool for simulating a mixture of digital hardware models, developed by Zero ASIC. Models can be represented with RTL simulation, RTL implemented on FPGAs, C++, or Python, with inter-model communication happening over fixed, unidirectional connections that mimic how a real system would be wired together. Under the hood, Switchboard connections are implemented as shared-memory queues, making them quite fast: up to 1 GB/s bandwidth / 200 ns latency. Because the queues have a simple, standardized memory layout, they are convenient to access from RTL implemented on FPGAs. Switchboard powers the multi-chiplet cloud FPGA emulation system on Zero ASIC's website, where it is fast enough to boot Linux and run ML models on emulated hardware in near realtime. We also use Switchboard on a smaller scale for running Python-based block-level tests; its Universal Memory Interface API, combined with its low setup overhead, makes Switchboard an efficient way to write one-off tests. In other words, Switchboard is fast enough to run big workloads, but easy enough to use that it has become a go-to for daily hardware design tasks.

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