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CACE Study: Open source analog and mixed-signal design flow
--client
fossi
--show
latch_2024
--room b45r230 15384 --force
Next: 10 IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead
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Marks
Author(s):
Tim Edwards
Location
b45r230
Date
apr Sat 20
Days Raw Files
Start
16:00
First Raw Start
14:54
Duration
00:20:00
Offset
1:05:37
End
16:20
Last Raw End
15:54
Chapters
00:00
0:12:13
0:20:42
Total cuts_time
24 min.
https://fossi-foundation.org/latch-up/2024
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CACE_Study_Open_source_analog_and_mixedsignal_design_flow.json
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With the recent introduction of multiple open-source foundry process design kits (PDKs), open source digital flows for custom chip design have largely standardized around yosys and OpenROAD/openlane. Open source design flows for analog and mixed-signal circuits have lagged behind. Most designers use a combination of xschem, ngspice, klayout, and magic. But there is little standardization of project structure, specification, testbench methodology, and datasheet generation. The CACE system, originally designed for the Efabless platform, addresses the need for a system around the specification of circuit performance, with a standard way to simulate circuits over all process, voltage, and temperature corners, and automatically collate results into a datasheet of electrical and physical parameters with maximum/typical/minimum values, pass/fail results, and tables and graphs on demand. This presentation explores the capabilities of CACE and looks at current and future development directions.
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production notes
2024-04-20/14_54_23.ts
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