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id
conf
start
state
episode.name
per New York Times Manual of Style
cmt
released
yt
mp4
14800
2
Sat 04 09:30
12
Diagrams and system visualisation in chip design
Diagrams and System Visualisation in Chip Design
Y
Y
14801
3
Sat 04 10:00
8
Netlistsvg: How to Draw a Better Schematic than Graphviz
Netlistsvg: How to Draw a Better Schematic Than Graphviz
Y
Y
14802
4
Sat 04 10:50
12
Lessons learned customising the Rocket RISC-V core
Lessons Learned Customising the Rocket RISC-V Core
Y
Y
14803
5
Sat 04 11:10
8
Higher-Order Hardware Design with Chisel 3
Higher-Order Hardware Design With Chisel 3
Y
Y
14804
6
Sat 04 11:40
8
The fusion of high-level synthesis with event-oriented hardware description (myhdl)
The Fusion of High-level Synthesis With Event-oriented Hardware Description (Myhdl)
Y
Y
14806
8
Sat 04 13:50
8
OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh
OpenPiton+Ariane: Making Ariane Multicore With OpenPiton’s P-Mesh
N
Y
14807
9
Sat 04 14:10
8
Lessons Learned from Open-Sourcing NVDLA
Lessons Learned From Open-Sourcing NVDLA
N
Y
14809
11
Sat 04 15:30
12
Live Graph infrastructure for Synthesis and Simulation
Live Graph Infrastructure for Synthesis and Simulation
Y
Y
14812
14
Sat 04 17:30
12
How I started learning FPGA: My journey writing a GameBoy in Verilog
How I Started Learning FPGA: My Journey Writing a GameBoy in Verilog
Y
Y
14813
15
Sat 04 18:00
12
Emulation of vintage integrated circuits through die analysis and reverse-EDA
Emulation of Vintage Integrated Circuits Through Die Analysis and Reverse-EDA
Y
Y
14814
16
Sat 04 18:20
0
Mingle, drinks
Mingle, Drinks
N
14815
17
Sun 05 09:30
8
BaseJump STL: a Standard Template Library for Hardware Design
BaseJump STL: A Standard Template Library for Hardware Design
Y
Y
14817
19
Sun 05 10:30
8
Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
Verifying Open-Source Silicon With SystemVerilog: Getting in on the Ground Floor
Y
Y
14827
Sun 05 12:01
12
Tim has too many projects - LatchUp Edition
Tim Has Too Many Projects - LatchUp Edition
Y
Y
14820
22
Sun 05 13:20
12
FuseSoC - Cores have never been so much fun
FuseSoC - Cores Have Never Been So Much Fun
Y
Y
14821
23
Sun 05 13:50
12
DUH: document and tools for HW design reuse
DUH: Document and Tools for HW Design Reuse
Y
Y
14824
26
Sun 05 15:40
0
SYZYGY: An Open Standard For Semiconductor Evaluation
SYZYGY: An Open Standard for Semiconductor Evaluation
Y
14825
27
Sun 05 16:00
12
Open-Source FPGA tools, how and why?
Open-Source FPGA Tools, How and Why?
Y
Y
Veyepar
Video Eyeball Processor and Review