| id |
conf |
start |
state |
len
| episode.name
per New York Times Manual of Style
episode.slug
|
cmt |
released |
yt
mp4 |
| 15222 |
1 |
Fri 31 13:30 |
10 |
97 |
FireSim: A Scalable Platform for FPGA-Accelerated Simulation, Debugging, Profiling of RTL Designs
FireSim: A Scalable Platform for FPGA-Accelerated Simulation, Debugging, Profiling of RTL Designs
FireSim_A_Scalable_Platform_for_FPGAAccelerated_Simulation_Debugging_and_Profiling_of_RTL_Designs
|
|
Y |
Y
|
| 15223 |
2 |
Fri 31 14:00 |
10 |
53 |
bsg_tag: A minimal open-source ASIC configuration bus
Bsg_tag: A Minimal Open-source ASIC Configuration Bus
bsg_tag_A_minimal_opensource_ASIC_configuration_bus
|
|
Y |
Y
|
| 15224 |
3 |
Fri 31 15:00 |
10 |
51 |
OmniXtend: coherent scaleout over commodity fabrics
OmniXtend: Coherent Scaleout Over Commodity Fabrics
OmniXtend_coherent_scaleout_over_commodity_fabrics
|
|
Y |
Y
|
| 15225 |
4 |
Fri 31 15:30 |
10 |
56 |
Hammer: A Modular and Reusable Physical Design Flow Tool
Hammer: A Modular and Reusable Physical Design Flow Tool
Hammer_A_Modular_and_Reusable_Physical_Design_Flow_Tool
|
|
Y |
Y
|
| 15226 |
5 |
Fri 31 16:00 |
10 |
49 |
CIRCT: Open Source Circuit IR Compilers and Tools
CIRCT: Open Source Circuit IR Compilers and Tools
CIRCT_Open_Source_Circuit_IR_Compilers_and_Tools
|
|
Y |
Y
|
| 15227 |
6 |
Fri 31 17:00 |
10 |
31 |
Accelerating Chisel Development
Accelerating Chisel Development
Accelerating_Chisel_Development
|
|
Y |
Y
|
| 15228 |
7 |
Fri 31 17:30 |
10 |
34 |
Open-Source HW Commercial Adoption
Open-Source HW Commercial Adoption
OpenSource_HW_Commercial_Adoption
|
|
Y |
Y
|
| 15229 |
8 |
Sat 01 08:30 |
10 |
52 |
A UCSC Professor's path through Open-Source Hardware
A UCSC Professor's Path Through Open-Source Hardware
A_UCSC_Professors_path_through_OpenSource_Hardware
|
|
Y |
Y
|
| 15230 |
9 |
Sat 01 08:55 |
0 |
36 |
So You Want to be an Open Sourcerer?
So You Want to Be an Open Sourcerer?
So_You_Want_to_be_an_Open_Sourcerer
|
|
Y |
|
| 15232 |
40 |
Sat 01 08:55 |
10 |
31 |
If You Build It, Who Will Come?
If You Build It, Who Will Come?
If_You_Build_It_Who_Will_Come
|
|
Y |
Y
|
| 15233 |
41 |
Sat 01 09:20 |
10 |
62 |
Yet Another UCSC Professor’s path through Open-Source Hardware
Yet Another UCSC Professor’s Path Through Open-Source Hardware
Yet_Another_UCSC_Professors_path_through_OpenSource_Hardware
|
|
Y |
Y
|
| 15234 |
42 |
Sat 01 09:45 |
10 |
68 |
Tapeout-in-a-Semester: The Organization of Berkeley's Tapeout Course
Tapeout-in-a-Semester: The Organization of Berkeley's Tapeout Course
TapeoutinaSemester_The_Organization_of_Berkeleys_Tapeout_Course
|
|
Y |
Y
|
| 15254 |
29 |
Sat 01 10:10 |
10 |
24 |
Fearless Hardware Design
Fearless Hardware Design
Fearless_Hardware_Design
|
|
Y |
Y
|
| 15235 |
10 |
Sat 01 11:00 |
10 |
51 |
Minimax - a Compressed-First, Microcoded RISC-V CPU
Minimax - a Compressed-First, Microcoded RISC-V CPU
Minimax_a_CompressedFirst_Microcoded_RISCV_CPU
|
|
Y |
Y
|
| 15236 |
11 |
Sat 01 11:30 |
10 |
61 |
Open Source Brain-Inspired Neuromorphic Software and Hardware
Open Source Brain-Inspired Neuromorphic Software and Hardware
Open_Source_BrainInspired_Neuromorphic_Software_and_Hardware
|
|
Y |
Y
|
| 15255 |
-1 |
Sat 01 12:57 |
10 |
86 |
Gdsfactory, an Open Source python flow for circuit design, verification and validation
Gdsfactory, an Open Source Python Flow for Circuit Design, Verification and Validation
Gdsfactory_an_Open_Source_python_flow_for_circuit_design_verification_and_validation
|
|
Y |
Y
|
| 15237 |
12 |
Sat 01 13:00 |
10 |
65 |
RISu064 - An in-order non-blocking dual-issue RISC-V 64 processor
RISu064 - an In-order Non-blocking Dual-issue RISC-V 64 Processor
RISu064_An_inorder_nonblocking_dualissue_RISCV_64_processor
|
|
Y |
Y
|
| 15238 |
13 |
Sat 01 13:03 |
10 |
71 |
SimCommand: A High-Performance RTL Testbench API with Fork/Join Support
SimCommand: A High-Performance RTL Testbench API With Fork/Join Support
SimCommand_A_HighPerformance_RTL_Testbench_API_with_ForkJoin_Support
|
|
Y |
Y
|
| 15239 |
14 |
Sat 01 13:06 |
10 |
51 |
A radically simple 1-bit single-die "supercomputer"
A Radically Simple 1-bit Single-die "Supercomputer"
A_radically_simple_1bit_singledie_supercomputer
|
|
Y |
Y
|
| 15240 |
15 |
Sat 01 13:09 |
10 |
38 |
All Your OSS Codebase Are Belong To Us
All Your OSS Codebase Are Belong to Us
All_Your_OSS_Codebase_Are_Belong_To_Us
|
|
Y |
Y
|
| 15241 |
16 |
Sat 01 13:12 |
10 |
53 |
A Modular Approach to Variable Pipeline Depth Designs
A Modular Approach to Variable Pipeline Depth Designs
A_Modular_Approach_to_Variable_Pipeline_Depth_Designs
|
|
Y |
Y
|
| 15242 |
17 |
Sat 01 13:15 |
10 |
47 |
Open-source Hardware for Real-Time Applications
Open-source Hardware for Real-Time Applications
Opensource_Hardware_for_RealTime_Applications
|
|
Y |
Y
|
| 15243 |
18 |
Sat 01 13:18 |
10 |
46 |
An open-source robotics applications interface
An Open-source Robotics Applications Interface
An_opensource_robotics_applications_interface
|
|
Y |
Y
|
| 15256 |
50 |
Sat 01 13:21 |
10 |
78 |
DSAGEN: Democratizing Domain-Specific Accelerator Generation for FPGA Overlays
DSAGEN: Democratizing Domain-Specific Accelerator Generation for FPGA Overlays
DSAGEN_Democratizing_DomainSpecific_Accelerator_Generation_for_FPGA_Overlays
|
|
Y |
Y
|
| 15257 |
51 |
Sat 01 13:24 |
10 |
49 |
Educational Framework for Functional Verification
Educational Framework for Functional Verification
Educational_Framework_for_Functional_Verification
|
|
Y |
Y
|
| 15258 |
52 |
Sat 01 13:27 |
10 |
36 |
Using CVA6 in Architecture Education
Using CVA6 in Architecture Education
Using_CVA6_in_Architecture_Education
|
|
Y |
Y
|
| 15244 |
19 |
Sat 01 13:30 |
4 |
83 |
Open tools for an open standard: Control/status register automation using SystemRDL
Open Tools for an Open Standard: Control/status Register Automation Using SystemRDL
Open_tools_for_an_open_standard_Controlstatus_register_automation_using_SystemRDL
|
|
N |
|
| 15245 |
20 |
Sat 01 14:00 |
10 |
36 |
Goodbye Make, Hello SiliconCompiler!
Goodbye Make, Hello SiliconCompiler!
Goodbye_Make_Hello_SiliconCompiler
|
|
Y |
Y
|
| 15246 |
21 |
Sat 01 15:00 |
10 |
52 |
Chipyard: An Open-Source RISC-V SoC Design Framework
Chipyard: An Open-Source RISC-V SoC Design Framework
Chipyard_An_OpenSource_RISCV_SoC_Design_Framework
|
|
Y |
Y
|
| 15247 |
22 |
Sat 01 15:30 |
10 |
33 |
SVA based Checker IP in Verilator
SVA Based Checker IP in Verilator
SVA_based_Checker_IP_in_Verilator
|
|
Y |
Y
|
| 15248 |
23 |
Sat 01 16:00 |
10 |
93 |
Quality of Life with Virtual Prototypes - Open Source Tools in the Ecosystem of the RISC-V VP
Quality of Life With Virtual Prototypes - Open Source Tools in the Ecosystem of the RISC-V VP
Quality_of_Life_with_Virtual_Prototypes_Open_Source_Tools_in_the_Ecosystem_of_the_RISCV_VP
|
|
Y |
Y
|
| 15249 |
24 |
Sun 02 09:00 |
10 |
79 |
Constellation: A Open-Source Chisel Generator for Network-on-Chip Interconnects
Constellation: A Open-Source Chisel Generator for Network-on-Chip Interconnects
Constellation_A_OpenSource_Chisel_Generator_for_NetworkonChip_Interconnects
|
|
Y |
Y
|
| 15250 |
25 |
Sun 02 09:30 |
10 |
65 |
SystemVerilog-Style Constraints and Functional Coverage in Python
SystemVerilog-Style Constraints and Functional Coverage in Python
SystemVerilogStyle_Constraints_and_Functional_Coverage_in_Python
|
|
Y |
Y
|
| 15251 |
26 |
Sun 02 10:00 |
10 |
49 |
OpenROAD - Turning Designs into Optimized Silicon
OpenROAD - Turning Designs Into Optimized Silicon
OpenROAD_Turning_Designs_into_Optimized_Silicon
|
|
Y |
Y
|
| 15253 |
28 |
Sun 02 11:00 |
10 |
59 |
Space - Opportunities, Challenges for Open Source Community
Space - Opportunities, Challenges for Open Source Community
Space_Opportunities_Challenges_for_Open_Source_Community
|
|
Y |
Y
|
| 15252 |
27 |
Sun 02 11:00 |
10 |
43 |
Online Waveform viewer. Why do we need one?
Online Waveform Viewer. Why Do We Need One?
Online_Waveform_viewer_Why_do_we_need_one
|
|
Y |
Y
|