veyepar: Hammer: A Modular and Reusable Physical Design Flow Tool

Author(s):	Nayiri Krzysztofowicz
Location	UCSB Henley Hall room 1010
Date	mar Fri 31	Days Raw Files
Start	15:30	First Raw Start	15:04
Duration	00:20:00	Offset	0:25:40
End	15:50	Last Raw End	16:04
Chapters	00:00 0:07:49 0:08:41 0:18:30 0:26:37
Total cuts_time	27 min.

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Process technology scaling and hardware architecture specialization have vastly increased the need for chip design space exploration, while optimizing for power, performance, and area. Hammer is an open-source, reusable physical design flow generator that reduces design effort and increases portability by enforcing a separation among design-, tool-, and process technology-specific concerns via a modular software architecture. In this talk, we will outline Hammer's structure and highlight recent extensions that support both physical chip designers and hardware architects evaluating the merit and feasibility of their proposed designs. An evaluation of chip designs in process technologies ranging from 130nm down to 12nm across a series of RISC-V-based chips shows how Hammer-generated flows are reusable and enable efficient optimization for diverse applications. We will then highlight a fully-open-source RTL-to-GDS case study: using Hammer to implement a tapeout-ready Chipyard-generated RISC-V SoC in the Skywater 130nm process using the open-source EDA tools Yosys and OpenROAD.

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