veyepar: Constellation: A Open-Source Chisel Generator for Network-on-Chip Interconnects

Author(s):	Jerry Zhao
Location	UCSB Henley Hall room 1010
Date	apr Sun 02	Days Raw Files
Start	09:00	First Raw Start	09:12
Duration	00:20:00	Offset	0:12:41
End	09:20	Last Raw End	10:12
Chapters	00:00 0:28:06 0:29:20
Total cuts_time	35 min.

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In response to growing application diversity, System-on-Chip (SoC) architectures have become increasingly heterogeneous, with diverse cores and accelerators, as well as non-uniform memory systems. However, existing open-source design frameworks for SoCs and NoCs (Network-on-Chips) have been unable to facilitate design exploration of heterogeneous SoC architectures with irregular NoCs. We present Constellation, a new NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures. Constellation implements a highly decoupled specification system that allows an architect to specify an exponentially large design space of irregular virtual-channel wormhole-routed NoC architectures. Additionally, Constellation provides a diverse set of systems, regression tests, and evaluation tools to provide confidence in the correctness and performance of the generated hardware. Constellation is open-sourced and integrated into the Chipyard SoC design framework, allowing full-system exploration of heterogeneous SoC architectures with irregular memory fabrics.

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