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Open source RTL verification with Verilator
--client
fossi
--show
latch_2024
--room b45r230 15370 --force
Next: 10 Sonata: A development platform to enable exploring the use of CHERI for embedded applications
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Marks
Author(s):
Karol Gugala
Location
b45r230
Date
apr Sat 20
Days Raw Files
Start
09:00
First Raw Start
07:56
Duration
00:20:00
Offset
1:03:06
End
09:20
Last Raw End
08:56
Chapters
00:00
0:21:29
0:21:54
Total cuts_time
24 min.
https://fossi-foundation.org/latch-up/2024
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This presentation follows up on the [ORConf 2023](https://orconf.org/) [UVM support overview talk](https://orconf.org/#open-source-design-testing-and-verification-with-uvm-and-verilator) and discusses Antmicro's work towards enabling constrained randomization in Verilator, another important milestone on the road towards full open source UVM support. Ultimately, the work is meant to enable cloud scaling of production-grade ASIC verification workloads. With the new implementation, Verilator generates expressions in the smtlib2 language, letting users pick between multiple solvers, and introduces no build time dependencies. This presentation will cover the details of the implementation, provide open source samples and discuss future considerations for open source RTL verification.
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