Hi user
Welcome - 8
FOSSi Foundation Update - 8
Diagrams and system visualisation in chip design - 12
Netlistsvg: How to Draw a Better Schematic than Graphviz - 8
Lessons learned customising the Rocket RISC-V core - 12
Higher-Order Hardware Design with Chisel 3 - 8
The fusion of high-level synthesis with event-oriented hardware description (myhdl) - 8
JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor - 8
OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh - 8
Lessons Learned from Open-Sourcing NVDLA - 8
DVKit: An Integrated Development Environment for Design and Verification Engineers - 8
Live Graph infrastructure for Synthesis and Simulation - 12
The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor - 8
FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud - 8
How I started learning FPGA: My journey writing a GameBoy in Verilog - 12
Emulation of vintage integrated circuits through die analysis and reverse-EDA - 12
Mingle, drinks - 0
BaseJump STL: a Standard Template Library for Hardware Design - 8
OSVVM, VHDL's #1 FPGA Verification Library - 12
Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor - 8
RISC-V in Debian - 12
Lightning Talks - 0
Hermes-Lite: Amateur Radio SDR - 12
Tim has too many projects - LatchUp Edition - 12
FuseSoC - Cores have never been so much fun - 12
DUH: document and tools for HW design reuse - 12
Nyuzi: An Open Source GPGPU Processor - 12
OpenRAM: An Open Source Memory Compiler - 12
SYZYGY: An Open Standard For Semiconductor Evaluation - 0
Open-Source FPGA tools, how and why? - 12
Veyepar Video Eyeball Processor and Review