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id
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start
state
episode.name
per New York Times Manual of Style
episode.slug
cmt
released
yt
mp4
14798
0
Sat 04 09:00
8
Welcome
Welcome
Welcome_11
N
Y
14799
1
Sat 04 09:10
8
FOSSi Foundation Update
FOSSi Foundation Update
FOSSi_Foundation_Update
N
Y
14800
2
Sat 04 09:30
12
Diagrams and system visualisation in chip design
Diagrams and System Visualisation in Chip Design
Diagrams_and_system_visualisation_in_chip_design
Y
Y
14801
3
Sat 04 10:00
8
Netlistsvg: How to Draw a Better Schematic than Graphviz
Netlistsvg: How to Draw a Better Schematic Than Graphviz
Netlistsvg_How_to_Draw_a_Better_Schematic_than_Graphviz
Y
Y
14802
4
Sat 04 10:50
12
Lessons learned customising the Rocket RISC-V core
Lessons Learned Customising the Rocket RISC-V Core
Lessons_learned_customising_the_Rocket_RISCV_core
Y
Y
14803
5
Sat 04 11:10
8
Higher-Order Hardware Design with Chisel 3
Higher-Order Hardware Design With Chisel 3
HigherOrder_Hardware_Design_with_Chisel_3
Y
Y
14804
6
Sat 04 11:40
8
The fusion of high-level synthesis with event-oriented hardware description (myhdl)
The Fusion of High-level Synthesis With Event-oriented Hardware Description (Myhdl)
The_fusion_of_highlevel_synthesis_with_eventoriented_hardware_description_myhdl
Y
Y
14805
7
Sat 04 13:30
8
JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor
JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor
JuxtaPiton_The_First_OpenSource_HeterogeneousISA_Processor
Y
Y
14806
8
Sat 04 13:50
8
OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh
OpenPiton+Ariane: Making Ariane Multicore With OpenPiton’s P-Mesh
OpenPitonAriane_Making_Ariane_Multicore_with_OpenPitons_PMesh
N
Y
14807
9
Sat 04 14:10
8
Lessons Learned from Open-Sourcing NVDLA
Lessons Learned From Open-Sourcing NVDLA
Lessons_Learned_from_OpenSourcing_NVDLA
N
Y
14808
10
Sat 04 14:30
8
DVKit: An Integrated Development Environment for Design and Verification Engineers
DVKit: An Integrated Development Environment for Design and Verification Engineers
DVKit_An_Integrated_Development_Environment_for_Design_and_Verification_Engineers
Y
Y
14809
11
Sat 04 15:30
12
Live Graph infrastructure for Synthesis and Simulation
Live Graph Infrastructure for Synthesis and Simulation
Live_Graph_infrastructure_for_Synthesis_and_Simulation
Y
Y
14810
12
Sat 04 16:00
8
The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor
The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor
The_BerkeleyOutofOrderMachine_An_Open_Source_Synthesizable_HighPerformance_RISCV_Processor
Y
Y
14811
13
Sat 04 16:30
8
FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud
FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud
FireSim_OpenSource_Easytouse_FPGAAccelerated_CycleExact_Hardware_Simulation_in_the_Cloud
Y
Y
14812
14
Sat 04 17:30
12
How I started learning FPGA: My journey writing a GameBoy in Verilog
How I Started Learning FPGA: My Journey Writing a GameBoy in Verilog
How_I_started_learning_FPGA_My_journey_writing_a_GameBoy_in_Verilog
Y
Y
14813
15
Sat 04 18:00
12
Emulation of vintage integrated circuits through die analysis and reverse-EDA
Emulation of Vintage Integrated Circuits Through Die Analysis and Reverse-EDA
Emulation_of_vintage_integrated_circuits_through_die_analysis_and_reverseEDA
Y
Y
14814
16
Sat 04 18:20
0
Mingle, drinks
Mingle, Drinks
Mingle_drinks
N
14815
17
Sun 05 09:30
8
BaseJump STL: a Standard Template Library for Hardware Design
BaseJump STL: A Standard Template Library for Hardware Design
BaseJump_STL_a_Standard_Template_Library_for_Hardware_Design
Y
Y
14816
18
Sun 05 10:00
12
OSVVM, VHDL's #1 FPGA Verification Library
OSVVM, VHDL's #1 FPGA Verification Library
OSVVM_VHDLs_1_FPGA_Verification_Library
Y
Y
14817
19
Sun 05 10:30
8
Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
Verifying Open-Source Silicon With SystemVerilog: Getting in on the Ground Floor
Verifying_OpenSource_Silicon_with_SystemVerilog_Getting_in_on_the_Ground_Floor
Y
Y
14818
20
Sun 05 11:20
12
RISC-V in Debian
RISC-V in Debian
RISCV_in_Debian
Y
Y
14819
21
Sun 05 11:40
0
Lightning Talks
Lightning Talks
Lightning_Talks_29
N
14826
Sun 05 11:49
12
Hermes-Lite: Amateur Radio SDR
Hermes-Lite: Amateur Radio SDR
hermes_lite
Y
Y
14827
Sun 05 12:01
12
Tim has too many projects - LatchUp Edition
Tim Has Too Many Projects - LatchUp Edition
tim_has_many_projects_latchup_edition
Y
Y
14820
22
Sun 05 13:20
12
FuseSoC - Cores have never been so much fun
FuseSoC - Cores Have Never Been So Much Fun
FuseSoC_Cores_have_never_been_so_much_fun
Y
Y
14821
23
Sun 05 13:50
12
DUH: document and tools for HW design reuse
DUH: Document and Tools for HW Design Reuse
DUH_document_and_tools_for_HW_design_reuse
Y
Y
14822
24
Sun 05 14:20
12
Nyuzi: An Open Source GPGPU Processor
Nyuzi: An Open Source GPGPU Processor
Nyuzi_An_Open_Source_GPGPU_Processor
Y
Y
14823
25
Sun 05 15:10
12
OpenRAM: An Open Source Memory Compiler
OpenRAM: An Open Source Memory Compiler
OpenRAM_An_Open_Source_Memory_Compiler
Y
Y
14824
26
Sun 05 15:40
0
SYZYGY: An Open Standard For Semiconductor Evaluation
SYZYGY: An Open Standard for Semiconductor Evaluation
SYZYGY_An_Open_Standard_For_Semiconductor_Evaluation
Y
14825
27
Sun 05 16:00
12
Open-Source FPGA tools, how and why?
Open-Source FPGA Tools, How and Why?
OpenSource_FPGA_tools_how_and_why
Y
Y
Veyepar
Video Eyeball Processor and Review