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title: Welcome
14798 Welcome_11.png

title: FOSSi Foundation Update
14799 FOSSi_Foundation_Update.png

title: Diagrams and system visualisation in chip design
authors: Aliaksei Chapyzhenka
14800 Diagrams_and_system_visualisation_in_chip_design.png

title: Netlistsvg: How to Draw a Better Schematic than Graphviz
authors: Neil Turley
14801 Netlistsvg_How_to_Draw_a_Better_Schematic_than_Graphviz.png

title: Lessons learned customising the Rocket RISC-V core
authors: Julius Baxter
14802 Lessons_learned_customising_the_Rocket_RISCV_core.png

title: Higher-Order Hardware Design with Chisel 3
authors: Jack Koenig
14803 HigherOrder_Hardware_Design_with_Chisel_3.png

title: The fusion of high-level synthesis with event-oriented hardware description (myhdl)
authors: Christopher Felton
14804 The_fusion_of_highlevel_synthesis_with_eventoriented_hardware_description_myhdl.png

title: JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor
authors: Katie Lim
14805 JuxtaPiton_The_First_OpenSource_HeterogeneousISA_Processor.png

title: OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh
authors: Jonathan Balkind
14806 OpenPitonAriane_Making_Ariane_Multicore_with_OpenPitons_PMesh.png

title: Lessons Learned from Open-Sourcing NVDLA
authors: Joshua Wise
14807 Lessons_Learned_from_OpenSourcing_NVDLA.png

title: DVKit: An Integrated Development Environment for Design and Verification Engineers
authors: Matthew Ballance
14808 DVKit_An_Integrated_Development_Environment_for_Design_and_Verification_Engineers.png

title: Live Graph infrastructure for Synthesis and Simulation
authors: Jose Renau
14809 Live_Graph_infrastructure_for_Synthesis_and_Simulation.png

title: The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor
authors: Jerry Zhao, Abe Gonzalez, Ben Korpan
14810 The_BerkeleyOutofOrderMachine_An_Open_Source_Synthesizable_HighPerformance_RISCV_Processor.png

title: FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud
authors: David Biancolin, Alon Amid
14811 FireSim_OpenSource_Easytouse_FPGAAccelerated_CycleExact_Hardware_Simulation_in_the_Cloud.png

title: How I started learning FPGA: My journey writing a GameBoy in Verilog
authors: Wenting Zhang
14812 How_I_started_learning_FPGA_My_journey_writing_a_GameBoy_in_Verilog.png

title: Emulation of vintage integrated circuits through die analysis and reverse-EDA
authors: Cole Johnson
14813 Emulation_of_vintage_integrated_circuits_through_die_analysis_and_reverseEDA.png

title: Mingle, drinks
14814 Mingle_drinks.png

title: BaseJump STL: a Standard Template Library for Hardware Design
authors: Daniel Petrisko
14815 BaseJump_STL_a_Standard_Template_Library_for_Hardware_Design.png

title: OSVVM, VHDL's #1 FPGA Verification Library
authors: Jim Lewis
14816 OSVVM_VHDLs_1_FPGA_Verification_Library.png

title: Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor
authors: Matthew Ballance
14817 Verifying_OpenSource_Silicon_with_SystemVerilog_Getting_in_on_the_Ground_Floor.png

title: RISC-V in Debian
authors: Vagrant Cascadian
14818 RISCV_in_Debian.png

title: Lightning Talks
14819 Lightning_Talks_29.png

title: Hermes-Lite: Amateur Radio SDR
authors: Steve Haynal
14826 hermes_lite.png

title: Tim has too many projects - LatchUp Edition
authors: Tim 'mithro' Ansell
14827 tim_has_many_projects_latchup_edition.png

title: FuseSoC - Cores have never been so much fun
authors: Olof Kindgren
14820 FuseSoC_Cores_have_never_been_so_much_fun.png

title: DUH: document and tools for HW design reuse
authors: Aliaksei Chapyzhenka
14821 DUH_document_and_tools_for_HW_design_reuse.png

title: Nyuzi: An Open Source GPGPU Processor
authors: Jeff Bush
14822 Nyuzi_An_Open_Source_GPGPU_Processor.png

title: OpenRAM: An Open Source Memory Compiler
authors: Matthew Guthaus
14823 OpenRAM_An_Open_Source_Memory_Compiler.png

title: SYZYGY: An Open Standard For Semiconductor Evaluation
authors: Tom McLeod
14824 SYZYGY_An_Open_Standard_For_Semiconductor_Evaluation.png

title: Open-Source FPGA tools, how and why?
authors: Piotr Esden-Tempski
14825 OpenSource_FPGA_tools_how_and_why.png

Veyepar Video Eyeball Processor and Review