Hi user
Admin Login:
status grid processes pipeline recording_sheets.pdf today's t+1 Reschedule schedule talk_intro.pdf title slides anomalies
client admin show admin episodes admin image_file admin play_list
Episode Count: 31
id loc name startend duration state episode.name episode.authors e/r cmt rel img rf host index
15356 b45r230 Fri 19 09:20 09:40 00:20:00 10 Caster: An Open-source E-Ink Controller Wenting Zhang y Y 13 Y
15357 b45r230 Fri 19 09:40 10:00 00:20:00 10 Teaching Modern EDA using a Tapeout-Centric University Course Anish Singhani y Y 11 Y
15358 b45r230 Fri 19 10:20 10:40 00:20:00 10 CedarEDA for open source silicon Keno Fischer y Y 10 Y
15359 b45r230 Fri 19 10:40 11:00 00:20:00 10 Cohort: Software-Oriented Acceleration for You, Me, and Our Heterogeneous SoCs Nazerke Turtayeva y Y 9 Y
15361 b45r230 Fri 19 10:53 11:13 00:20:00 10 Towards Cycle-accurate Simulation of xBGAS Jie Li y Y 8 Y
15360 b45r230 Fri 19 11:00 11:20 00:20:00 10 Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture Mert Side y Y 9 Y
15362 b45r230 Fri 19 12:40 13:00 00:20:00 10 Artifact Evaluation for the Field Programmable Gate Array Community Miriam Leeser y Y 10 Y
15363 b45r230 Fri 19 13:00 13:20 00:20:00 10 Chisel 6 and beyond Jack Koenig y Y 15 Y
15364 b45r230 Fri 19 13:20 13:40 00:20:00 10 MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL Tobias Strauch y Y 15 Y
15365 b45r230 Fri 19 14:20 14:40 00:20:00 10 Architecture 2.0: Toward Open Source Foundation Models and Datasets for Hardware Design Vijay Janapa Reddi, Shvetank Prakash y Y 9 Y
15366 b45r230 Fri 19 14:40 15:00 00:20:00 10 Riding The Wave: Building Wave Pipelines in FPGAs Rice Shelley y Y 12 Y
15367 b45r230 Fri 19 15:00 15:20 00:20:00 10 Giving Students A Byte of Open-Source: Advancing Hardware Education Ethan Sifferman y Y 8 Y
15368 b45r230 Fri 19 15:40 16:00 00:20:00 10 Open-source resources for learning the Bluespec HL-HDLs Rishiyur Nikhil y Y 12 Y
15369 b45r230 Fri 19 16:00 16:20 00:20:00 10 PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface Matt Ballance y Y 6 Y
15370 b45r230 Sat 20 09:00 09:20 00:20:00 10 Open source RTL verification with Verilator Karol Gugala y Y 15 Y
15371 b45r230 Sat 20 09:20 09:40 00:20:00 10 Sonata: A development platform to enable exploring the use of CHERI for embedded applications Hugo McNally y Y 15 Y
15372 b45r230 Sat 20 09:40 10:00 00:20:00 10 Transparent Checkpointing for Fault Tolerance in RISC-V Aayushi Gautam y Y 20 Y
15373 b45r230 Sat 20 10:20 10:40 00:20:00 10 HDLAgent, Enhancing Hardware Language in the age of LLMs Jose Renau y Y 13 Y
15374 b45r230 Sat 20 10:40 11:00 00:20:00 10 Spade: An HDL Inspired By Modern Software Languages Frans Skarman y Y 11 Y
15375 b45r230 Sat 20 11:00 11:20 00:20:00 10 Switchboard: Calling All Hardware Models Steven Herbst y Y 11 Y
15376 b45r230 Sat 20 12:20 12:40 00:20:00 10 From an Open-Source ISA to Open-Source HW to Open-Source Silicon Luca Bertaccini y Y 7 Y
15377 b45r230 Sat 20 12:40 13:00 00:20:00 10 Open Source Hardware: Hacking Silicon for Fun (instead of profit) Troy Benjegerdes y Y 12 Y
15378 b45r230 Sat 20 13:00 13:20 00:20:00 10 A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation Steve Hoover y Y 9 Y
15379 b45r230 Sat 20 13:20 13:40 00:20:00 10 UMI: Universal Memory Interface Andreas Olofsson y Y 9 Y
15380 b45r230 Sat 20 14:20 14:40 00:20:00 10 ABC: The Way It Should Have Been Designed Alan Mishchenko y Y 6 Y
15381 b45r230 Sat 20 14:40 15:00 00:20:00 0 BYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development Ajeetha Kumari Venkatesan y Y 9
15382 b45r230 Sat 20 15:00 15:20 00:20:00 10 Beyond EDA lies Edalize Olof Kindgren y Y 9 Y
15383 b45r230 Sat 20 15:40 16:00 00:20:00 10 RF Front-end receiver design for 2.4GH/5GHz WiFi application Jabeom Koo y Y 9 Y
15384 b45r230 Sat 20 16:00 16:20 00:20:00 10 CACE Study: Open source analog and mixed-signal design flow Tim Edwards y Y 10 Y
15385 b45r230 Sat 20 16:20 16:40 00:20:00 10 IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead Frank Vater y Y 10 Y
15386 b45r230 Sat 20 16:40 17:00 00:20:00 10 Tiny Tapeout: custom silicon open to all Pat Deegan y Y 9 Y

Veyepar Video Eyeball Processor and Review