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VenCaf b45r230
Fri 19
09:20 [_] Caster: An Open-source E-Ink Controller
09:40 [_] Teaching Modern EDA using a Tapeout-Centric University Course
10:20 [_] CedarEDA for open source silicon
10:40 [_] Cohort: Software-Oriented Acceleration for You, Me, and Our Heterogeneous SoCs
10:53 [_] Towards Cycle-accurate Simulation of xBGAS
11:00 [_] Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture
12:40 [_] Artifact Evaluation for the Field Programmable Gate Array Community
01:00 [_] Chisel 6 and beyond
01:20 [_] MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL
02:20 [_] Architecture 2.0: Toward Open Source Foundation Models and Datasets for Hardware Design
02:40 [_] Riding The Wave: Building Wave Pipelines in FPGAs
03:00 [_] Giving Students A Byte of Open-Source: Advancing Hardware Education
03:40 [_] Open-source resources for learning the Bluespec HL-HDLs
04:00 [_] PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface
06:00 [_] Building an Ecosystem for Hardware Generators
06:14 [_] Tim's Silicon Presentations
06:18 [_] Surfer - An Extensible and Snappy Waveform Viewer
06:21 [_] Clean up your EDA flows with tclint
06:24 [_] Attempts to design hardware using dafny
06:27 [_] Zeno: An Open-Source Scalable Capability-Based Secure Architecture
06:29 [_] Accelerating Hardware Design with Custom GPTs
06:32 [_] OSHHISS Open Source for Hybrid Hetrogenous Integrated Semiconductor Systems
06:35 [_] Where Community Powers Innovation
06:40 [_] CoreScore like never before
06:43 [_] ChipWhisperer: Past & Future of a FPGA-based Research Tool
07:07 [_] clock
VenCaf b45r230
Sat 20
09:00 [_] Open source RTL verification with Verilator
09:20 [_] Sonata: A development platform to enable exploring the use of CHERI for embedded applications
09:40 [_] Transparent Checkpointing for Fault Tolerance in RISC-V
10:20 [_] HDLAgent, Enhancing Hardware Language in the age of LLMs
10:40 [_] Spade: An HDL Inspired By Modern Software Languages
11:00 [_] Switchboard: Calling All Hardware Models
12:20 [_] From an Open-Source ISA to Open-Source HW to Open-Source Silicon
12:40 [_] Open Source Hardware: Hacking Silicon for Fun (instead of profit)
01:00 [_] A History of TL-Verilog Google Summer of Code Projects under FOSSi Foundation
01:20 [_] UMI: Universal Memory Interface
02:20 [_] ABC: The Way It Should Have Been Designed
02:40 [_] BYOL (Build Your Own Linter) – UVMLint for IEEE-UVM core code development
03:00 [_] Beyond EDA lies Edalize
03:40 [_] RF Front-end receiver design for 2.4GH/5GHz WiFi application
04:00 [_] CACE Study: Open source analog and mixed-signal design flow
04:20 [_] IHP Open Source PDK: Announcement, Setup, Current State and Experiences, and look ahead
04:40 [_] Tiny Tapeout: custom silicon open to all

Veyepar Video Eyeball Processor and Review