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UCSB Henley Hall room 1010 VenCaf b45r230
Fri 31
01:30 [_] FireSim: A Scalable Platform for FPGA-Accelerated Simulation, Debugging, Profiling of RTL Designs
02:00 [_] bsg_tag: A minimal open-source ASIC configuration bus
03:00 [_] OmniXtend: coherent scaleout over commodity fabrics
03:30 [_] Hammer: A Modular and Reusable Physical Design Flow Tool
04:00 [_] CIRCT: Open Source Circuit IR Compilers and Tools
05:00 [_] Accelerating Chisel Development
05:30 [_] Open-Source HW Commercial Adoption
UCSB Henley Hall room 1010 VenCaf b45r230
Sat 01
08:30 [_] A UCSC Professor's path through Open-Source Hardware
08:55 [_] If You Build It, Who Will Come?
09:20 [_] Yet Another UCSC Professor’s path through Open-Source Hardware
09:45 [_] Tapeout-in-a-Semester: The Organization of Berkeley's Tapeout Course
10:10 [_] Fearless Hardware Design
11:00 [_] Minimax - a Compressed-First, Microcoded RISC-V CPU
11:30 [_] Open Source Brain-Inspired Neuromorphic Software and Hardware
12:57 [_] Gdsfactory, an Open Source python flow for circuit design, verification and validation
01:00 [_] RISu064 - An in-order non-blocking dual-issue RISC-V 64 processor
01:03 [_] SimCommand: A High-Performance RTL Testbench API with Fork/Join Support
01:06 [_] A radically simple 1-bit single-die "supercomputer"
01:09 [_] All Your OSS Codebase Are Belong To Us
01:12 [_] A Modular Approach to Variable Pipeline Depth Designs
01:15 [_] Open-source Hardware for Real-Time Applications
01:18 [_] An open-source robotics applications interface
01:21 [_] DSAGEN: Democratizing Domain-Specific Accelerator Generation for FPGA Overlays
01:24 [_] Educational Framework for Functional Verification
01:27 [_] Using CVA6 in Architecture Education
01:30 [_] Open tools for an open standard: Control/status register automation using SystemRDL
02:00 [_] Goodbye Make, Hello SiliconCompiler!
03:00 [_] Chipyard: An Open-Source RISC-V SoC Design Framework
03:30 [_] SVA based Checker IP in Verilator
04:00 [_] Quality of Life with Virtual Prototypes - Open Source Tools in the Ecosystem of the RISC-V VP
UCSB Henley Hall room 1010 VenCaf b45r230
Sun 02
09:00 [_] Constellation: A Open-Source Chisel Generator for Network-on-Chip Interconnects
09:30 [_] SystemVerilog-Style Constraints and Functional Coverage in Python
10:00 [_] OpenROAD - Turning Designs into Optimized Silicon
11:00 [_] Online Waveform viewer. Why do we need one?

Veyepar Video Eyeball Processor and Review