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Episode Count: 17
id loc name startend duration state episode.name episode.authors e/r cmt rel img rf host index
14798 Revolution Hall Sat 04 09:00 09:10 0:10:0 8 Welcome N 7 Y
14799 Revolution Hall Sat 04 09:10 09:30 0:20:0 8 FOSSi Foundation Update N 13 Y
14800 Revolution Hall Sat 04 09:30 10:00 0:30:0 12 Diagrams and system visualisation in chip design Aliaksei Chapyzhenka y Y 16 Y
14801 Revolution Hall Sat 04 10:00 10:30 0:30:0 8 Netlistsvg: How to Draw a Better Schematic than Graphviz Neil Turley y Y 11 Y
14802 Revolution Hall Sat 04 10:50 11:10 0:20:0 12 Lessons learned customising the Rocket RISC-V core Julius Baxter y Y 6 Y
14803 Revolution Hall Sat 04 11:10 11:40 0:30:0 8 Higher-Order Hardware Design with Chisel 3 Jack Koenig y Y 9 Y
14804 Revolution Hall Sat 04 11:40 12:10 0:30:0 8 The fusion of high-level synthesis with event-oriented hardware description (myhdl) Christopher Felton y Y 6 Y
14805 Revolution Hall Sat 04 13:30 13:50 0:20:0 8 JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor Katie Lim y Y 4 Y
14806 Revolution Hall Sat 04 13:50 14:10 0:20:0 8 OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh Jonathan Balkind y N 8 Y
14807 Revolution Hall Sat 04 14:10 14:30 0:20:0 8 Lessons Learned from Open-Sourcing NVDLA Joshua Wise y N 10 Y
14808 Revolution Hall Sat 04 14:30 14:50 0:20:0 8 DVKit: An Integrated Development Environment for Design and Verification Engineers Matthew Ballance y Y 10 Y
14809 Revolution Hall Sat 04 15:30 16:00 0:30:0 12 Live Graph infrastructure for Synthesis and Simulation Jose Renau y Y 8 Y
14810 Revolution Hall Sat 04 16:00 16:30 0:30:0 8 The Berkeley-Out-of-Order-Machine: An Open Source Synthesizable High-Performance RISC-V Processor Jerry Zhao, Abe Gonzalez, Ben Korpan Y 10 Y
14811 Revolution Hall Sat 04 16:30 17:00 0:30:0 8 FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud David Biancolin, Alon Amid Y 7 Y
14812 Revolution Hall Sat 04 17:30 18:00 0:30:0 12 How I started learning FPGA: My journey writing a GameBoy in Verilog Wenting Zhang y Y 10 Y
14813 Revolution Hall Sat 04 18:00 18:30 0:30:0 12 Emulation of vintage integrated circuits through die analysis and reverse-EDA Cole Johnson y Y 14 Y
14814 Revolution Hall Sat 04 18:20 18:50 0:30:0 0 Mingle, drinks N 11

Veyepar Video Eyeball Processor and Review