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Episode Count: 14
id
loc name
start
end
duration
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episode.authors
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15356
b45r230
Fri 19 09:20
09:40
00:20:00
10
Caster: An Open-source E-Ink Controller
Wenting Zhang
y
Y
13
Y
15357
b45r230
Fri 19 09:40
10:00
00:20:00
10
Teaching Modern EDA using a Tapeout-Centric University Course
Anish Singhani
y
Y
11
Y
15358
b45r230
Fri 19 10:20
10:40
00:20:00
10
CedarEDA for open source silicon
Keno Fischer
y
Y
10
Y
15359
b45r230
Fri 19 10:40
11:00
00:20:00
10
Cohort: Software-Oriented Acceleration for You, Me, and Our Heterogeneous SoCs
Nazerke Turtayeva
y
Y
9
Y
15361
b45r230
Fri 19 10:53
11:13
00:20:00
10
Towards Cycle-accurate Simulation of xBGAS
Jie Li
y
Y
8
Y
15360
b45r230
Fri 19 11:00
11:20
00:20:00
10
Towards xBGAS on CHERI: Examining the Benefits of a Secure Distributed Architecture
Mert Side
y
Y
9
Y
15362
b45r230
Fri 19 12:40
13:00
00:20:00
10
Artifact Evaluation for the Field Programmable Gate Array Community
Miriam Leeser
y
Y
10
Y
15363
b45r230
Fri 19 13:00
13:20
00:20:00
10
Chisel 6 and beyond
Jack Koenig
y
Y
15
Y
15364
b45r230
Fri 19 13:20
13:40
00:20:00
10
MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL
Tobias Strauch
y
Y
15
Y
15365
b45r230
Fri 19 14:20
14:40
00:20:00
10
Architecture 2.0: Toward Open Source Foundation Models and Datasets for Hardware Design
Vijay Janapa Reddi, Shvetank Prakash
y
Y
9
Y
15366
b45r230
Fri 19 14:40
15:00
00:20:00
10
Riding The Wave: Building Wave Pipelines in FPGAs
Rice Shelley
y
Y
12
Y
15367
b45r230
Fri 19 15:00
15:20
00:20:00
10
Giving Students A Byte of Open-Source: Advancing Hardware Education
Ethan Sifferman
y
Y
8
Y
15368
b45r230
Fri 19 15:40
16:00
00:20:00
10
Open-source resources for learning the Bluespec HL-HDLs
Rishiyur Nikhil
y
Y
12
Y
15369
b45r230
Fri 19 16:00
16:20
00:20:00
10
PyHDL-IF: An Easy-to-Use Python/HDL Cross-Calling Interface
Matt Ballance
y
Y
6
Y
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