| status grid processes pipeline | recording_sheets.pdf today's t+1 Reschedule | schedule talk_intro.pdf | title slides | anomalies | |
| client admin | show admin | episodes admin | image_file admin | play_list |
| id | loc name | start | end | duration | state | episode.name | episode.authors | e/r | cmt | rel | img | rf | host | index |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 14800 | Revolution Hall | Sat 04 09:30 | 10:00 | 0:30:0 | 12 | Diagrams and system visualisation in chip design | Aliaksei Chapyzhenka | y | Y | 16 | Y | |||
| 14802 | Revolution Hall | Sat 04 10:50 | 11:10 | 0:20:0 | 12 | Lessons learned customising the Rocket RISC-V core | Julius Baxter | y | Y | 6 | Y | |||
| 14809 | Revolution Hall | Sat 04 15:30 | 16:00 | 0:30:0 | 12 | Live Graph infrastructure for Synthesis and Simulation | Jose Renau | y | Y | 8 | Y | |||
| 14812 | Revolution Hall | Sat 04 17:30 | 18:00 | 0:30:0 | 12 | How I started learning FPGA: My journey writing a GameBoy in Verilog | Wenting Zhang | y | Y | 10 | Y | |||
| 14813 | Revolution Hall | Sat 04 18:00 | 18:30 | 0:30:0 | 12 | Emulation of vintage integrated circuits through die analysis and reverse-EDA | Cole Johnson | y | Y | 14 | Y |
Veyepar Video Eyeball Processor and Review