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Episode Count: 24
id loc name startend duration state episode.name episode.authors e/r cmt rel img rf host index
14800 Revolution Hall Sat 04 09:30 10:00 0:30:0 12 Diagrams and system visualisation in chip design Aliaksei Chapyzhenka y Y 16 Y
14801 Revolution Hall Sat 04 10:00 10:30 0:30:0 8 Netlistsvg: How to Draw a Better Schematic than Graphviz Neil Turley y Y 11 Y
14802 Revolution Hall Sat 04 10:50 11:10 0:20:0 12 Lessons learned customising the Rocket RISC-V core Julius Baxter y Y 6 Y
14803 Revolution Hall Sat 04 11:10 11:40 0:30:0 8 Higher-Order Hardware Design with Chisel 3 Jack Koenig y Y 9 Y
14804 Revolution Hall Sat 04 11:40 12:10 0:30:0 8 The fusion of high-level synthesis with event-oriented hardware description (myhdl) Christopher Felton y Y 6 Y
14805 Revolution Hall Sat 04 13:30 13:50 0:20:0 8 JuxtaPiton: The First Open-Source, Heterogeneous-ISA Processor Katie Lim y Y 4 Y
14806 Revolution Hall Sat 04 13:50 14:10 0:20:0 8 OpenPiton+Ariane: Making Ariane Multicore with OpenPiton’s P-Mesh Jonathan Balkind y N 8 Y
14807 Revolution Hall Sat 04 14:10 14:30 0:20:0 8 Lessons Learned from Open-Sourcing NVDLA Joshua Wise y N 10 Y
14808 Revolution Hall Sat 04 14:30 14:50 0:20:0 8 DVKit: An Integrated Development Environment for Design and Verification Engineers Matthew Ballance y Y 10 Y
14809 Revolution Hall Sat 04 15:30 16:00 0:30:0 12 Live Graph infrastructure for Synthesis and Simulation Jose Renau y Y 8 Y
14812 Revolution Hall Sat 04 17:30 18:00 0:30:0 12 How I started learning FPGA: My journey writing a GameBoy in Verilog Wenting Zhang y Y 10 Y
14813 Revolution Hall Sat 04 18:00 18:30 0:30:0 12 Emulation of vintage integrated circuits through die analysis and reverse-EDA Cole Johnson y Y 14 Y
14815 Revolution Hall Sun 05 09:30 10:00 0:30:0 8 BaseJump STL: a Standard Template Library for Hardware Design Daniel Petrisko y Y 7 Y
14816 Revolution Hall Sun 05 10:00 10:30 0:30:0 12 OSVVM, VHDL's #1 FPGA Verification Library Jim Lewis y Y 10 Y
14817 Revolution Hall Sun 05 10:30 11:00 0:30:0 8 Verifying Open-Source Silicon with SystemVerilog: Getting in on the Ground Floor Matthew Ballance y Y 8 Y
14818 Revolution Hall Sun 05 11:20 11:40 0:20:0 12 RISC-V in Debian Vagrant Cascadian y Y 10 Y
14826 Revolution Hall Sun 05 11:49 12:01 00:12:00 12 Hermes-Lite: Amateur Radio SDR Steve Haynal y Y 10 Y
14827 Revolution Hall Sun 05 12:01 12:29 00:28:00 12 Tim has too many projects - LatchUp Edition Tim 'mithro' Ansell y Y 11 Y
14820 Revolution Hall Sun 05 13:20 13:50 0:30:0 12 FuseSoC - Cores have never been so much fun Olof Kindgren y Y 4 Y
14821 Revolution Hall Sun 05 13:50 14:20 0:30:0 12 DUH: document and tools for HW design reuse Aliaksei Chapyzhenka y Y 10 Y
14822 Revolution Hall Sun 05 14:20 14:50 0:30:0 12 Nyuzi: An Open Source GPGPU Processor Jeff Bush y Y 9 Y
14823 Revolution Hall Sun 05 15:10 15:40 0:30:0 12 OpenRAM: An Open Source Memory Compiler Matthew Guthaus y Y 12 Y
14824 Revolution Hall Sun 05 15:40 16:10 0:30:0 0 SYZYGY: An Open Standard For Semiconductor Evaluation Tom McLeod y Y 14
14825 Revolution Hall Sun 05 16:00 16:20 0:20:0 12 Open-Source FPGA tools, how and why? Piotr Esden-Tempski y Y 6 Y

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